Backward Fault Analysis for Electronic Circuit Masking Factors
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Solution Overview
Problem
Existing methods for determining fault observability in electronic circuits are limited, particularly in digital semiconductor circuits, as they fail to accurately account for complex masking effects like FDD and TDD, and are restricted to CPU registers, lacking generality for synchronous semiconductor circuits, with high computational expense and limited applicability.
Innovation Solution
A method that determines fault observability by simulating the behavior of electronic circuits using a model similar to real hardware, focusing on storage elements and their logical connections, and employing backward simulation to identify sensitive paths and relevance markings, reducing computational expense and accounting for various masking effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional methods are used to determine fault observability, then the analysis is limited to CPU registers and cannot account for complex masking effects like FDD and TDD, but extending the analysis to all storage elements and logic circuits increases computational expense
Solution Approach 1:
The patent extends the fault observability analysis from CPU registers to all types of storage elements and logic circuits, creating a universal method that applies to flip-flops, SRAM blocks, and other digital circuit components. This multi-functional approach allows the same analysis technique to handle diverse circuit architectures without requiring separate methods for each circuit type.
Solution Approach 2:
The patent segments the circuit analysis into distinct components: storage elements, logic circuits, and signal paths. By breaking down the complex circuit into these manageable segments and analyzing each separately while tracking their interactions, the method reduces the computational complexity of analyzing the entire circuit as a single complex system.
2Measurement precision
If backward simulation is employed to identify sensitive paths and relevance markings, then fault masking factors can be precisely determined, but the simulation process requires detailed modeling of circuit behavior
Solution Approach 1:
The patent employs backward simulation, which inverts the conventional forward-time simulation approach. Instead of propagating faults forward through the circuit and observing where they manifest, the method traces backward from potential fault locations to identify which faults would be observable at given outputs. This inversion simplifies the analysis by directly identifying sensitive paths without requiring complex forward propagation simulations.
Solution Approach 2:
The patent extracts the essential behavior characteristics of the circuit into a simplified simulation model that captures only the relevant aspects needed for fault observability analysis. By taking out and isolating the critical behavioral elements (storage element transitions, logic gate operations, signal dependencies), the method creates a manageable model that provides precise fault masking factor determination without requiring complete detailed modeling of all circuit aspects.
3Reliability
If all storage elements and logic circuits are analyzed for fault observability, then comprehensive fault detection capability is achieved, but the computational burden increases significantly
Solution Approach 1:
The patent applies local quality analysis by evaluating fault observability for each storage element and logic circuit individually, determining which specific components can potentially mask faults and which cannot. By assigning different analysis depths and computational efforts to different circuit elements based on their local fault masking characteristics, the method achieves comprehensive fault detection capability while minimizing overall computational burden by not treating all components equally.
Data Source
AI summary
A method and a system for determining the observability of faults in an electronic circuit include a processor that simulates, in a simulation phase, a behavior of the electronic circuit using a simulation model, and that determined, in an analysis phase, based on the simulation, and for each of a plurality of elements of the electronic circuit, time periods in which an occurrent fault could cause a deviation in analysis output signals, where the occurrent fault is determined not to cause any deviation in output signals in other time periods.