Backward Verification of Multi-Stage Hardware Stall Independence
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Solution Overview
Problem
Verifying the stall independence of hardware designs for multi-stage components is complex and often infeasible due to the requirement of detailed understanding of the component's operation, especially for complex designs, as existing methods require working through the design stage by stage to ensure data movement and validity across stages.
Innovation Solution
A method and system that verify stall independence by working backwards from the final stage, checking that the output data remains consistent across stages with minimal sequences of inputs, allowing for verification without understanding the internal workings of the component, using formal verification tools to formally verify properties related to data transformations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing verification methods work through the design stage by stage to ensure data movement and validity, then verification thoroughness is improved, but verification complexity and difficulty increase significantly
Solution Approach 1:
The patent applies inversion by reversing the traditional verification approach. Instead of verifying from the first stage through to the final stage, the method verifies from the final stage backwards to the first stage. This is achieved by assuming values at the final stage and working backwards through each preceding stage to verify consistency, thereby simplifying the verification process while maintaining thoroughness.
Solution Approach 2:
The patent uses copying by creating a copy of the hardware design for verification purposes. The verification method operates on this copied representation, allowing thorough verification without directly complicating the original design. The copy enables systematic backward verification while preserving the original design integrity.
2Measurement precision
If existing verification methods require detailed understanding of the component's internal operation, then measurement precision is improved, but ease of operation deteriorates
Solution Approach 1:
The patent eliminates the need for detailed understanding of internal operations by inverting the verification approach. Instead of requiring verifiers to trace through complex internal stage-by-stage operations forward, the method starts from the final stage and works backwards, requiring understanding only of input-output relationships at each stage rather than internal workings.
Solution Approach 2:
The patent creates a verification copy of the design that abstracts away complex internal operations. This copy enables precise verification of data transformations while hiding implementation details, making the verification process easier to perform without sacrificing precision.
3Reliability
If formal verification tools are used to verify stall independence, then verification reliability is improved, but convergence difficulty increases
Solution Approach 1:
The patent significantly improves formal verification tool convergence by inverting the verification direction. Traditional forward verification from first to final stage creates complex state-space exploration that tools struggle with. The backward verification approach reduces this complexity by constraining the search space, allowing tools to converge more reliably on stall independence properties.
Data Source
AI summary
Methods and systems for verifying a hardware design for a multi-stage component configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled is stall independent. For each stage from the second stage to the last stage: a relevant portion of the output data of an instantiation of the hardware design is verified as the same if the instantiation is in the same state when that stage is enabled in a cycle by any set of inputs and any subsequent stages are enabled in subsequent cycles by a first minimal sequence of inputs. The relevant portion of the output data of the hardware design is verified as the same if the instantiation is in the same state (i) when that stage is enabled in a cycle and any subsequent stages are enabled in subsequent cycles by a second minimal sequence of inputs and (ii) when that stage is stalled, then that stage is enabled in the next cycle and the subsequent stages are enabled in subsequent cycles by the second minimal sequence of inputs.