Crossbar Error Coalescing for Multi-Bit Memory ECC
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Solution Overview
Problem
Random bit errors in memories negatively impact the robustness and availability of computer systems, as existing technologies fail to effectively manage and correct these errors across multiple bit positions within a codeword.
Innovation Solution
A programmable crossbar matrix or array of steering multiplexors coalesces data from multiple 'bad' bit positions into a single codeword symbol, using error mapping information to configure the routing logic at boot or initialization time, thereby improving error detection and correction by concentrating unreliability into a single symbol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data from multiple bad bit positions is scattered across multiple codeword symbols, then the memory system can store more data, but error detection and correction capabilities are reduced
Solution Approach 1:
The patent merges multiple unreliable bit positions from different data symbols into a single check symbol. The coalescing logic consolidates error-prone bits that would otherwise be distributed across multiple codeword symbols, allowing the error correction system to handle them as a concentrated group. This merging improves reliability by enabling more effective error detection and correction while managing complexity through systematic consolidation.
2Productivity
If unreliable bits are distributed across multiple symbols, then codeword structure is maintained, but error correction efficiency decreases
Solution Approach 1:
The patent applies preliminary action by identifying and mapping unreliable bit positions before data storage and retrieval operations. During initialization or boot-up, the system performs memory training to detect bad bits and creates an error map. This pre-characterization of unreliable positions allows the coalescing logic to efficiently route these bits during normal operations, improving error correction efficiency without losing track of error mapping information.
Solution Approach 2:
The patent introduces an intermediary coalescing logic layer between the memory array and the error correction decoder. This intermediary component receives codewords, identifies unreliable bits using pre-stored error mapping information, and redirects them to a consolidated check symbol before passing the modified codeword to the decoder. This mediator improves error correction efficiency by preprocessing the data to concentrate errors, while the error mapping information serves as the intermediary knowledge base enabling this process.
3Measurement precision
If error coalescing is implemented, then error detection capability is improved, but additional circuitry is required
Solution Approach 1:
The patent segments the error coalescing function into distinct modular components: bad bit identification logic, routing/steering logic, and coalescing logic. Each segment handles a specific aspect of the error management process. This segmentation improves error detection precision by allowing each component to be optimized independently, while managing device complexity through modular design that enables reuse and systematic integration.
Data Source
AI summary
A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.