Bad Memory Block Utilization via Enhanced Parity Distribution
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Solution Overview
Problem
Memory devices like NAND flash and PCRAM have limited write operations per cell, leading to reduced lifespan when write operations are concentrated, and bad memory blocks are typically excluded due to errors, reducing their operational lifespan and storage capacity.
Innovation Solution
A memory system that includes normal and bad memory blocks, where data and parity codes are distributed across multiple bad blocks to enable error correction, allowing for reliable use of bad blocks by generating and storing parity codes across multiple pages within these blocks, ensuring data integrity and extending device lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bad memory blocks are excluded from use, then data reliability is maintained, but storage capacity and device lifespan are reduced
Solution Approach 1:
The patent applies this principle by converting bad memory blocks (harmful elements) into usable storage resources. Through enhanced error correction codes and multi-block data distribution, previously unusable bad blocks are transformed into functional storage capacity, thereby increasing overall storage capacity while maintaining data reliability.
Solution Approach 2:
The patent changes the error correction parameters by using enhanced error correction codes with more parity bits compared to conventional codes. This parameter change enables the system to handle higher error rates in bad memory blocks, allowing their utilization while preserving data integrity.
2Quantity of substance
If enhanced error correction is applied to bad memory blocks, then storage capacity is increased, but device complexity increases
Solution Approach 1:
The patent segments data and error correction codes across multiple memory blocks. By distributing data bits and parity bits across different blocks (including bad blocks), the system manages complexity through modular organization rather than requiring a completely different approach, making the enhanced error correction more tractable.
Solution Approach 2:
The patent introduces an intermediary layer of enhanced error correction coding between the data and the bad memory blocks. This intermediary mechanism (the enhanced ECC system) mediates the interaction between reliable data storage requirements and the unreliable bad blocks, translating one into the other through sophisticated but manageable error correction processes.
3Speed
If write operations are concentrated on specific cell regions, then write speed is improved, but device lifespan is reduced
Solution Approach 1:
The patent implements dynamic address mapping that can adaptively allocate write operations across different memory blocks including bad blocks. This dynamic allocation prevents concentration of write operations on specific cell regions, distributing wear more evenly and extending device lifespan while maintaining efficient write performance through optimized block selection.
Data Source
AI summary
A memory device is provided. The memory device includes a plurality of normal memory blocks; and at least two or more bad memory blocks, wherein data having the same number of bits as data to be stored in a normal memory block and a parity code having the number of bits at least twice greater than that of a parity code to be stored in the normal memory block are stored in a first bad memory block and a second bad memory block among the bad memory blocks.