Balanced 8T SRAM Cell With CFET Port Partitioning
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Solution Overview
Problem
Existing SRAM designs face challenges in achieving scalability and performance due to disparities in logic and memory cell density, particularly with complementary field-effect transistor (CFET) technology, where nMOS transistors are stronger than pMOS transistors, leading to inefficient write operations.
Innovation Solution
Implementing a balanced 8T SRAM cell with four nMOSFETs and four pMOSFETs, optimizing the write port with nMOS and read ports with pMOS to achieve high density and symmetry, using CFET process for vertical stacking, and enabling reconfigurable port configurations for improved write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional SRAM designs are used, then read operations can be performed, but write operations become inefficient due to nMOS being stronger than pMOS
Solution Approach 1:
The patent applies asymmetry by creating an unbalanced transistor configuration where the write port uses only nMOS transistors while read ports use pMOS transistors. This asymmetric design leverages the stronger nMOS for write operations to overcome the inherent weakness of pMOS in drive strength, thereby improving write operation efficiency and stability without requiring symmetric nMOS-pMOS pairing in all ports.
2Quantity of substance
If CFET technology is used for vertical stacking, then device density increases, but manufacturing complexity increases
Solution Approach 1:
The patent segments the SRAM cell into distinct functional regions with specific transistor types placed in designated locations. The write port is segmented to use only nMOS transistors while read ports use only pMOS transistors, allowing the CFET manufacturing process to be simplified by targeting specific transistor types for specific functions rather than requiring complex mixed-type integration throughout the entire cell.
3Speed
If nMOS write port is used, then write speed improves, but power consumption increases
Solution Approach 1:
The patent applies local quality by optimizing the write port with nMOS transistors specifically for high-speed write operations, while maintaining pMOS transistors in read ports for stable reading. This localized optimization allows the write path to benefit from nMOS speed advantages without requiring the entire SRAM cell to operate at high power, thereby improving write speed while managing overall power consumption through selective transistor placement.
Data Source
AI summary
Embodiments herein relate to a balanced eight-transistor (8T) static random-access memory (SRAM) cell having four n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) and four p-type MOSFETS. An nMOS write port and two pMOS read ports are optimized with a complementary field-effect transistor (CFET) process to achieve a high density. The cell is reconfigurable for various port configurations including 1R1W (1-read 1-write), 2R1W (2-read 1-write), 3R1W (3-read 1-write), 4R1W (4-read 1-write) and single/dual-ported SRAM with appropriate Vt (voltage threshold) targeting.