Balanced Cell-Based Differential Logic for FPGA Cryptography
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Cryptography circuits, particularly in FPGA technology, are vulnerable to differential power analysis attacks due to inherent imperfections in physical systems, leading to information leaks and security breaches, despite existing countermeasures like differential logic which increase complexity and are not designed to resist attacks effectively.
Innovation Solution
The implementation of Balanced Cell-Based Differential Logic (BCDL) that includes a synchronization phase before precharge and evaluation phases, using memory-based cells and unanimity cells to ensure all input signals are synchronized, eliminating anticipated evaluation issues and technological differences, thereby balancing power consumption and enhancing resistance to attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If differential logic is used to counter attacks by measuring electrical consumption, then power consumption becomes independent of data, but the complexity of the cryptographic circuit is more than doubled
Solution Approach 1:
The cryptographic circuit is divided into two separate differential networks operating in parallel. Each network processes one component of the dual-rail encoded inputs, allowing independent optimization and reducing the complexity burden on a single network while maintaining the security benefits of differential logic
Solution Approach 2:
Instead of trying to mask the data-dependent power consumption variations, the invention inverts the approach by encoding inputs in a way that ensures both possible values consume equal power. The dual-rail encoding with precharge and evaluation phases guarantees that regardless of the secret key value, the power consumption profile remains identical, thus eliminating the vulnerability to DPA attacks
2Reliability
If dual rail connections are used to ensure constant power consumption, then security against DPA is improved, but routing constraints and technological differences create logical biases that can be exploited
Solution Approach 1:
The invention applies different design optimizations to different parts of the differential network. Each network is independently optimized for its specific logic functions while maintaining the overall differential structure. This allows local adjustments that compensate for technological variations without compromising the global security properties
Solution Approach 2:
The invention changes the operational parameters of the differential network by introducing controlled delay elements and adjusting timing parameters. This ensures that signal propagation delays, which are inherently different due to technological variations, are compensated for, eliminating the logical biases that attackers could exploit while maintaining constant power consumption
3Adaptability or versatility
If FPGAs are used for cryptography applications requiring flexibility, then adaptability to changing standards is improved, but vulnerability to side channel attacks increases
Solution Approach 1:
The invention creates a universal protective layer that can be applied to any cryptographic algorithm implemented in FPGA. The differential logic structure and dual-rail encoding are algorithm-agnostic, allowing the same security mechanism to protect diverse cryptographic standards while maintaining the FPGAs inherent flexibility and reconfigurability
Data Source
Figure 1~3
Figure 4~6
Figure 7~9
AI summary
A programmable cryptography circuit includes memory-based cells defining the logic function of each cell, integrating a differential network capable of carrying out calculations on pairs of binary variables, including a first network of cells implementing logic functions on the first component of the pairs and a second network of dual cells operating in complementary logic on the second component of the pair. A calculation step includes a precharge phase, in which the variables are put into a known state at the output of the cells, and an evaluation phase in which a calculation is made by the cells. A phase of synchronizing the variables is inserted before the evaluation phase or the precharge phase in each cell capable of receiving several signals conveying input variables, the synchronization being carried out on the most delayed signal.