Balanced Clock Duty-Cycle Correction for Jitter Reduction
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Solution Overview
Problem
Differential clocks in integrated circuits often experience duty cycle distortion and non-idealities, leading to deterministic jitter in DDR systems and suboptimal operation in flip-flops, particularly when transitioning between current-mode logic (CML) and complementary metal oxide semiconductor (CMOS) logic.
Innovation Solution
A duty-cycle adjustment circuit that aligns rising and falling edges of output signals with corresponding edges of input signals to correct duty cycle, using pull-up and pull-down circuitry and delay stages to generate complementary clock signals with a 50% duty cycle, even when input signals have non-ideal duty cycles or are not balanced.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If differential clock signals are used in high-speed mixed-signal applications, then signaling speed and data transmission rate are improved, but duty cycle distortion and non-idealities occur leading to deterministic jitter
Solution Approach 1:
The patent introduces an intermediary duty cycle correction circuit between the CML clock source and the CMOS logic circuit. This intermediary circuit receives the distorted differential clock signals, corrects their duty cycles to 50%, and outputs clean complementary clock signals. The correction circuit acts as a mediator that isolates the upstream clock source from downstream logic requirements, eliminating deterministic jitter without requiring changes to either the source or load.
2Reliability
If duty cycle correction circuits are added to correct non-idealities, then clock signal quality and operation speed are improved, but device complexity and hardware resources increase
Solution Approach 1:
The duty cycle correction function is segmented into two independent but synchronized sub-circuits: a first clock generator that produces one phase of the differential output based on transitions in one input signal, and a second clock generator that produces the complementary phase based on transitions in the other input signal. Each generator is independently structured with its own pull-up and pull-down circuitry, but they share the same input differential pair and operate in lockstep. This segmentation allows for modular design, independent optimization, and reduced complexity compared to a monolithic correction circuit.
Data Source
AI summary
A duty-cycle adjustment circuit receives a differential pair of input signals and generates an output signal based on the differential pair. The duty-cycle adjustment circuit drives the output signal to a logic-high state based on transitions of a first polarity in a first input signal of the differential pair, and drives the output signal to a logic-low state based on transitions of the first polarity in a second input signal of the differential pair. For example, rising-edge transitions of the output signal may be aligned with rising-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with rising-edge transitions of the second input signal. Alternatively, rising-edge transitions of the output signal may be aligned with falling-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with falling-edge transitions of the second input signal.