Balanced Corrective Read for Cell-to-Cell Interference
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Solution Overview
Problem
Existing memory sub-systems face challenges in accurately addressing cell-to-cell interference, which can lead to increased errors and reduced reliability due to interference and lateral charge migration.
Innovation Solution
Implementing balanced corrective read operations by determining interference values for each adjacent cell state and assigning these states to bins based on their interference intervals, allowing for tailored read level offsets to account for interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional read operations are used without corrective measures, then device complexity is reduced and operation is simpler, but read accuracy deteriorates due to cell-to-cell interference
Solution Approach 1:
The system performs preliminary actions by reading adjacent cells before the target cell to determine interference levels, and by pre-calculating corrective read levels based on interference maps. This allows the actual read operation to be more accurate without requiring complex real-time interference compensation during the read itself.
Solution Approach 2:
The patent introduces an interference map as an intermediary data structure that stores interference level information between cells. This intermediary allows the system to account for cell-to-cell interference effects without directly implementing complex interference compensation circuitry, thereby improving read accuracy while controlling device complexity.
2Measurement precision
If corrective read operations are implemented to address cell-to-cell interference, then read accuracy is improved, but operation time increases
Solution Approach 1:
The system performs interference assessment and corrective level determination as preliminary actions before the actual read operation. By pre-calculating the necessary corrective read levels based on interference maps and adjacent cell states, the patent minimizes the time required during the actual read operation, thereby reducing overall operation time while maintaining high read accuracy.
3Reliability
If multiple read levels are used to compensate for interference, then read reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by determining corrective read levels specifically for each target cell based on its unique interference profile and adjacent cell states. Rather than using a uniform complex correction approach for all cells, the system tailors the read operation to the local interference conditions of each cell, thereby improving reliability without unnecessarily increasing overall device complexity.
Solution Approach 2:
The system changes the read level parameter dynamically based on interference conditions. By adjusting the read level offset according to the determined interference level and corrective read level, the patent achieves reliable reads across varying interference conditions without requiring multiple fixed read levels or complex hardware modifications, thus improving reliability while controlling device complexity.
Data Source
AI summary
An example memory device includes a memory array and processing logic to perform operations including: identifying, among a plurality of memory cells of the memory array, a target memory cell and a set of memory cells adjacent to the target memory cell, such that each memory cell of the set of memory cells is characterized by a respective memory cell state; determining, for each memory cell state, a respective interference value reflecting memory cell-to-memory cell interference; assigning, based on the respective interference value, each memory cell state to a respective bin of a set of state information bins; and determining a set of read level offsets for reading the target memory cell, such that each read level offset of the set of read level offsets is associated with a respective bin of the set of state information bins.