Balanced DICE Latch Circuit for SEU-Resistant Data Storage
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Solution Overview
Problem
Existing DICE latches are vulnerable to Single Event Upset (SEU) events due to imbalanced interlocked paths, leading to potential data corruption and reduced reliability in integrated circuits.
Innovation Solution
The DICE latch circuit incorporates two or more sub-latches, each coupled to a global output terminal through a respective output buffer, forming balanced interlocked paths to enhance resistance to SEU events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DICE latch structure is used, then device complexity is reduced, but reliability deteriorates due to vulnerability to SEU events
Solution Approach 1:
The latch is divided into two or more sub-latches (first sub-latch, second sub-latch) that are coupled in an interlocked manner. Each sub-latch processes the input signal independently but influences the other through shared feedback paths, creating balanced interlocked paths that resist SEU events while maintaining manageable complexity in each individual sub-latch unit.
Solution Approach 2:
Different sub-latches are configured with complementary transistor arrangements (e.g., first sub-latch with p-type and n-type transistors, second sub-latch with opposite configuration) to create local symmetry. This local quality differentiation ensures that SEU events affecting one sub-latch are compensated by the complementary structure of the other, improving overall reliability without requiring complete redesign of the entire latch system.
2Loss of information
If balanced interlocked paths are implemented, then data integrity is improved, but device complexity increases due to additional sub-latches and buffers
Solution Approach 1:
Multiple sub-latches are merged into a single unified latch structure where the first and second sub-latches share common input and output nodes. The sub-latches are interconnected through feedback paths that allow them to function as a cohesive unit, ensuring data integrity through redundant verification while avoiding the need for completely separate latch circuits.
Solution Approach 2:
The latch structure employs redundant sub-latches that replicate the basic latch functionality with complementary transistor configurations. Each sub-latch copies the essential storage function but with inverted or complementary logic paths, creating balanced interlocked paths that verify data integrity through multiple identical yet complementary operational paths.
3Reliability
If multiple sub-latches with output buffers are used, then FIT rate is reduced, but manufacturing complexity increases
Solution Approach 1:
The sub-latches are configured with asymmetric transistor arrangements relative to each other (e.g., first sub-latch with specific p-type and n-type transistor positioning, second sub-latch with mirrored or inverted positioning). This controlled asymmetry creates balanced interlocked paths that are sensitive to differential changes, improving FIT rate by detecting and correcting single-event upsets that would affect only one asymmetric path.
Data Source
AI summary
A circuit includes a first Dual Interlocked Storage Cell (DICE) component, a second DICE component, a third DICE component, and a fourth DICE component operatively coupled to one another as a loop. The first and second DICE components form a first sub-latch configured to receive an input signal, the third and fourth DICE components form a second sub-latch configured to receive the same input signal, the first sub-latch is configured to provide, at a first node, an intermediate signal based on the input signal, and the second sub-latch is configured to provide, at a second node, the same intermediate signal based on the input signal. The circuit includes a first inverter configured to logically invert the intermediate signal and provide, at a third node, an output signal. The circuit includes a second inverter configured to logically invert the intermediate signal and provide, at the third node, the output signal.