Balanced Cell Drive Polarity for Side-Channel Resistant Circuits
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Solution Overview
Problem
Electronic circuits are vulnerable to side-channel attacks due to variations in current consumption during logic state transitions, which can reveal sensitive information and compromise data security.
Innovation Solution
The implementation of additional inverters in the signal network between driving and driven cells to balance capacitive loads, ensuring that current consumption is independent of logic state transitions, thereby reducing the circuit's sensitivity to power analysis attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional inverters are placed in the signal network to balance capacitive loads, then current consumption becomes independent of logic state transitions, but device complexity increases
Solution Approach 1:
The patent changes the electrical parameters of the circuit by introducing inverters to balance capacitive loads. This modifies the current consumption characteristics to be independent of logic state transitions, thereby protecting against power analysis attacks while maintaining functional correctness
Solution Approach 2:
Inverters are introduced as intermediary elements in the signal network between driving and driven cells. These intermediaries balance the capacitive load by inverting the signal, ensuring that transitions always charge the same capacitive load regardless of the logic state, thus masking the true operational state from power analysis
2Reliability
If Dual Rail Precharge Logic is used to balance capacitive loads, then protection against power analysis attacks is achieved, but hardware must be doubled
Solution Approach 1:
Instead of duplicating the entire circuit as in DRP, this patent changes the parameter balancing approach by using inverters to equalize capacitive loads on existing signal paths. This achieves the same security effect without requiring duplicate hardware circuits
Solution Approach 2:
The patent extracts the essential protective function from the DRP approach - balancing capacitive loads - and implements it selectively using only the necessary inverters on critical signal paths rather than duplicating the entire circuit. This isolates and applies only the needed protective mechanism
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates power analysis attacks by making the circuit's current consumption invariant to state transitions, enhancing data security without the need for doubling hardware, as seen in Dual-rail Pre-charge Logic methods.
Implementation Method 1
The one or more inverters are placed in a signal network that connects the driving cell to the driven cells. The inverters are configured to balance, over the signal network, (i) a first capacitive load charged by electrical currents caused by transitions from the first logic state to the second logic state and (ii) a second capacitive load charged by electrical currents caused by transitions from the second logic state to the first logic state.
Data Source
AI summary
An electronic circuit includes a driving cell, one or more driven cells and one or more inverters. The driving cell has two or more inputs and at least one output and is configured to toggle the output between first and second logic states in response to the inputs. Each driven cell has two or more inputs, of which at least one input is configured to be driven by the output of the driving cell. The one or more inverters are placed in a signal network that connects the driving cell to the driven cells. The inverters are configured to balance, over the signal network, (i) a first capacitive load charged by electrical currents caused by transitions from the first logic state to the second logic state and (ii) a second capacitive load charged by electrical currents caused by transitions from the second logic state to the first logic state.