Error Correction Logic Using Balanced Group Codes for Faster ECC
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing error detection and correction circuits in electronic systems are limited by propagation delays, which restrict data processing rates and storage efficiency, particularly when using Hamming codes for error correction.
Innovation Solution
The implementation of an error correction code system that generates check bits and detects bit errors using logic circuits derived from group codes separated by a Hamming distance with minimized population count variance, allowing for increased speed and reduced propagation delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum number of check bits are used for error detection and correction, then storage requirements are reduced, but propagation delays increase and data processing rates decrease
Solution Approach 1:
The patent changes the parameter of group code selection by minimizing population count variance among group codes. This optimization modifies the logical structure of the error detection circuit to reduce propagation delays while maintaining efficient storage utilization through balanced code distribution.
Solution Approach 2:
The patent applies local quality optimization by specifically targeting the population count characteristic of group codes. By ensuring uniform population counts across different group codes, the circuit achieves balanced signal propagation paths, thereby reducing overall propagation delay without affecting the minimum check bit requirement.
2Device complexity
If circuits use minimum hamming distance for error detection and correction, then the number of check bits is minimized, but propagation delays in error detection circuits increase
Solution Approach 1:
The patent optimizes the logical parameters of group codes by minimizing population count variance. This parameter optimization reduces the propagation delay in error detection circuits while maintaining the minimum hamming distance requirement, thereby achieving faster error detection without increasing the number of check bits.
Solution Approach 2:
The patent performs preliminary optimization of group code selection during the circuit design phase. By pre-selecting group codes with minimized population count variance, the circuit is configured to achieve reduced propagation delays from the outset, without requiring additional check bits or increasing device complexity.
3Speed
If group codes have same population count, then propagation delays are reduced and speed is increased, but selection constraints and device complexity increase
Solution Approach 1:
The patent applies parameter optimization by selecting group codes with uniform population counts. This constraint on the population count parameter ensures balanced propagation paths in the error detection circuit, achieving increased speed while the selection process itself becomes a systematic design procedure rather than an ad hoc process.
Data Source
AI summary
An error correction code system includes an error correction code generator for generating an error correction code based on a data unit and an error detector for detecting at least one bit error in the data unit based on the error correction code. The error correction code generator includes logic circuits for generating check bits in the error correction code. The error detector includes logic circuits for identifying any data bits of the data unit having a bit error based on the error correction code. The logic circuits in the error correction code generator and the error detector are derived from group codes separated from each other by a hamming distance and having a same population count. The error correction code system may also include an error corrector for correcting error bits in the data unit.