Balanced Logic Gate Precharge for Side-Channel Leakage Masking
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Solution Overview
Problem
Existing methods for protecting sensitive data in microcircuit devices against attacks like Simple Power Analysis, Differential Power Analysis, and Electromagnetic Analysis are inadequate, as they still allow information leaks through logic gate switching patterns, which can be exploited by attackers.
Innovation Solution
A countermeasure method that involves modifying logic gates to be statistically balanced during a precharge phase by forcing all inputs except one to a specific value, using multiplexers and transistors to change the gate's functionality into a buffer or inverter, ensuring the output signal has a 50% probability of being 0 or 1, thereby masking the data processing patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a precharge phase with random binary data is supplied to logic circuit inputs, then the logic gates are activated to process data, but the output of unbalanced logic gates (AND, NAND, OR, NOR) exhibits statistical imbalance that leaks information through power consumption and electromagnetic radiation variations
Solution Approach 1:
The patent changes the statistical parameter of logic gate outputs by introducing balanced logic gates that produce statistically balanced outputs regardless of input data values. This transforms the harmful statistical imbalance into a secure balanced state, preventing information leakage while maintaining normal logic processing functionality.
Solution Approach 2:
The patent introduces balanced logic gates as intermediary elements between unbalanced logic gates and the external environment. These balanced gates act as mediators that process the statistically imbalanced signals from unbalanced gates and transform them into statistically balanced outputs, thereby preventing information leakage without affecting the underlying data processing logic.
2Productivity
If statistically unbalanced logic gates (AND, NAND, OR, NOR) are used for data processing, then the circuit performs logical operations efficiently, but the switching patterns reveal information about processed data through SPA, DPA, and EMA attacks
Solution Approach 1:
The patent changes the output distribution parameter of logic gates by replacing unbalanced gates with balanced alternatives. The balanced logic gates maintain the same logical functionality but produce uniformly distributed outputs, thereby eliminating the statistical patterns that attackers exploit while preserving computational efficiency.
Solution Approach 2:
The patent segments the logic circuit into two distinct layers: unbalanced logic gates that perform the actual data processing operations, and balanced logic gates that process the outputs of unbalanced gates. This segmentation allows the circuit to maintain computational efficiency in the first layer while preventing information leakage in the second layer.
3Object-affected harmful factors
If logic gates are modified to be statistically balanced during precharge phase, then information leakage is reduced, but the circuit complexity increases due to additional multiplexers and control logic
Solution Approach 1:
The patent designs balanced logic gates that can operate in multiple modes: they function as standard logic gates during normal operation and as statistical balancers during precharge phases. This multi-functionality allows a single circuit structure to provide both computational functionality and security protection, reducing the need for separate dedicated security circuits.
Solution Approach 2:
The patent applies balanced logic gates during the precharge phase before actual data processing occurs. This preliminary action ensures that the circuit is in a statistically balanced state before sensitive operations begin, preventing information leakage from the outset without affecting the subsequent data processing functionality.
Data Source
AI summary
A countermeasure in a logic circuit having a logic gate supplying a binary output signal, the method including supplying binary data having random values to inputs of logic circuit during a precharge phase; supplying data to process to inputs of the logic circuit during a data processing phase; supplying on input of the logic circuit a precharge command signal launching a precharge phase; and under the effect of the precharge command signal, adapting the functioning of a logic gate of the logic circuit, statistically unbalanced, so that the output signal of the logic gate is in a binary state with a same probability as the random binary data supplied on input of the logic circuit during the precharge phase.