Balanced MOS N-Path Filter for Low-Distortion Area Efficiency
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Solution Overview
Problem
N-path filters face challenges in achieving area efficiency while avoiding nonlinear distortion, particularly when using MOS capacitors in bandpass networks, as their capacitance varies with voltage, leading to unwanted frequency response deviations.
Innovation Solution
The implementation of balanced MOS capacitors with complementary topology, where the capacitance of one side decreases as the other side increases, maintaining symmetry around a common-mode voltage, thereby minimizing even-order distortion and ensuring area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS capacitors are used in N-path filters to achieve area efficiency, then the filter occupies less chip area, but the capacitance varies with voltage causing nonlinear distortion
Solution Approach 1:
The patent applies asymmetry by using complementary MOS capacitors with opposite polarity configurations. One capacitor has its gate connected to the signal node while the other has its substrate connected to the signal node, creating asymmetric structures that compensate for each other's nonlinearities, thereby reducing even-order distortion while maintaining area efficiency
Solution Approach 2:
The patent changes the electrical parameters of the MOS capacitors by biasing them at different DC voltage levels. The complementary capacitors are biased at different voltages to operate in different regions of their capacitance-voltage characteristics, allowing the overall capacitance to remain more stable while maintaining area efficiency
2Speed
If larger capacitors are used to achieve narrow bandwidth, then the bandwidth is reduced, but the chip area increases
Solution Approach 1:
The patent uses asymmetric complementary MOS capacitor configurations where the different polarity capacitors provide complementary frequency responses. This allows the filter to achieve narrow bandwidth with smaller effective capacitance values, reducing the required chip area while maintaining the desired bandwidth characteristics
Solution Approach 2:
The patent employs N-path filter architecture with N parallel switch-capacitor circuits operating in continuous succession. The multi-phase switching ensures continuous signal processing, allowing the filter to achieve narrow bandwidth through time-averaging effects rather than requiring large static capacitance values, thus reducing chip area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for area-efficient N-path filters that maintain a symmetrical capacitance response to voltage changes, preventing even-order distortion and enabling their use in zero-IF receiver frontends without compromising performance.
Implementation Method 1
the respective balanced MOS capacitor exhibits a capacitance at the respective middle node with reference to a power supply node and a ground node
Data Source
AI summary
A N-path filter includes a plurality of switch-capacitor circuits controlled by a plurality of logical signals, respectively, and joined at a common shunt node, each of said switch-capacitor circuit comprising: a respective switch configured to controllably connect the common shunt node to a respective middle node in accordance with a respective logical signals among said plurality of logical signals; and a respective balanced MOS (metal oxide semiconductor) capacitor connected to the respective middle node, wherein the respective balanced MOS capacitor exhibits a capacitance at the respective middle node with reference to a power supply node and a ground node.