Balanced Semiconductor Package Wiring for Signal Integrity
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Solution Overview
Problem
As semiconductor packages become smaller and operate at higher speeds, signal integrity (SI) deteriorates due to noise and differences in wire lengths between semiconductor chips, leading to channel reflection and electrical characteristics degradation.
Innovation Solution
A balanced wiring structure is implemented in semiconductor packages, where the external connection terminal is connected to the bonding pad farthest from the chip stack, balancing channel lengths through the use of wiring lines, thereby minimizing signal reflection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor packages are made smaller and operate at higher speeds, then device capacity and operation speed are improved, but signal integrity deteriorates due to noise and wire length differences
Solution Approach 1:
The patent applies asymmetry by intentionally designing unequal physical distances from bonding pads to the external connection terminal, while compensating through wiring line routing to achieve equal electrical path lengths. The wiring lines are routed asymmetrically to balance the channel lengths, with longer wiring lines connecting to nearer bonding pads and shorter wiring lines to farther bonding pads, thereby resolving the signal integrity issue caused by asymmetric chip stacking.
2Quantity of substance
If multiple semiconductor chips are stacked to increase capacity, then device capacity is improved, but wire length differences cause channel reflection and electrical characteristics degradation
Solution Approach 1:
The patent changes the parameter of wiring line length to compensate for the asymmetric distances from bonding pads to the external connection terminal. By adjusting the wiring line lengths according to the position of each bonding pad, the patent achieves balanced channel lengths that prevent channel reflection and maintain stable electrical characteristics, thereby resolving the contradiction between increased device capacity through chip stacking and maintained electrical performance.
3Device complexity
If bonding pads are positioned closer to the chip stack to reduce wiring complexity, then device complexity is reduced, but wire length differences increase causing signal reflection
Solution Approach 1:
The patent introduces wiring lines as intermediary elements that mediate between the bonding pads and the external connection terminal. These wiring lines act as compensatory structures that equalize the electrical path lengths despite the asymmetric positioning of bonding pads, thereby preventing signal reflection while maintaining a relatively simple wiring structure concentrated on one side of the package substrate.
Data Source
AI summary
Provided is a semiconductor package having improved signal integrity (SI) and a chip stack structure of a plurality of semiconductor chips. The semiconductor package includes a package substrate, a chip stack structure on the package substrate and including at least two semiconductor chips, and an external connection terminal on a lower surface of the package substrate. A first semiconductor chip arranged uppermost in the chip stack structure is connected to a first bonding pad of the package substrate through a first wire. A second semiconductor chip arranged under the first semiconductor chip in the chip stack structure is connected to a second bonding pad of the package substrate through a second wire. When the first bonding pad is farther from the external connection terminal than the second bonding pad, the external connection terminal is connected to the first bonding pad through a wiring line of the package substrate.