Balanced Phase Detector Pre-Charging for High-Frequency Reliability
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Solution Overview
Problem
Conventional digital phase detectors struggle to provide reliable phase detection at high frequencies due to insufficient pre-charging of outputs during pre-charging periods, leading to unreliable phase detection results.
Innovation Solution
Incorporating a balancer configured with transistors to equalize the outputs of the phase detection circuit to a substantially the same voltage level during pre-charging periods, ensuring reliable phase detection across varying frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional digital phase detectors are used at high frequencies, then the operating frequency is increased, but the phase detection reliability deteriorates due to insufficient pre-charging of outputs
Solution Approach 1:
The patent applies preliminary action by pre-charging the outputs of the phase detection circuit to a predetermined voltage level before phase detection occurs. The pre-charging circuit actively charges the outputs during the pre-charging period, ensuring they reach the required voltage level in advance, which is critical for reliable operation at high frequencies where the pre-charging period is very short.
2Reliability
If the pre-charging period is extended to ensure reliable phase detection, then the phase detection accuracy is improved, but the operating speed deteriorates due to longer cycle time
Solution Approach 1:
The pre-charging circuit performs the voltage level preparation in advance during a dedicated pre-charging period, separating this function from the actual phase detection period. This allows the phase detection to occur quickly without waiting for gradual capacitor charging, thus maintaining high operating speed while ensuring accurate detection.
Solution Approach 2:
The pre-charging circuit acts as an intermediary between the clock signals and the phase detection circuit outputs. It actively manages the voltage levels of the outputs during the pre-charging period, ensuring they are properly prepared before phase detection begins, without interfering with the speed of the actual detection process.
3Device complexity
If passive RC time constant charging is used for pre-charging, then the circuit complexity is reduced, but the pre-charging speed deteriorates making it unsuitable for high frequencies
Solution Approach 1:
The patent replaces the passive RC time constant charging mechanism with an active pre-charging circuit that uses transistors to actively charge the outputs. This substitution of the charging mechanism enables much faster pre-charging speeds suitable for high-frequency operation, while the overall circuit complexity remains manageable through efficient design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reliable and accurate phase detection regardless of frequency, as demonstrated by simulations at 2 GHz and 3 GHz, where the outputs are consistently pre-charged to the same voltage level, improving detection accuracy.
Implementation Method 1
a balancer configured with transistors to equalize the outputs of the phase detection circuit to a substantially the same voltage level during pre-charging periods
Data Source
AI summary
Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the phase detection circuit for a phase detection. The phase detection circuit of one or more embodiments includes a cross-coupled latch configured to receive the two clock signals and generate a first latch output and a second latch output in response to the two clock signals. The aforementioned balancer is configured to substantially equalize the voltage levels of the first and second latch outputs before the phase detection circuit detects a phase difference between the two clock signals. For example, the balancer might pre-charge the outputs of the phase detection circuit to substantially the same voltage level before phase detection.