Balanced Phase Detector Output Pre-Charging for High-Frequency Clocks
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Solution Overview
Problem
Conventional digital phase detectors struggle to provide reliable phase detection at high frequencies due to insufficient pre-charging of outputs during pre-charging periods, leading to unreliable phase detection results.
Innovation Solution
Incorporating a balancer configured with transistors to equalize the outputs of the phase detection circuit to a substantially the same voltage level during pre-charging periods, ensuring reliable phase detection across various frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional digital phase detectors are used at high frequencies, then the detection speed increases, but the reliability of phase detection deteriorates due to insufficient pre-charging of outputs
Solution Approach 1:
The patent applies preliminary action by pre-charging the outputs of the phase detection circuit to a predetermined voltage level before phase detection occurs. The balancer circuit equalizes the voltage levels of both outputs during a pre-charging period, ensuring they start at identical levels before the actual phase detection event, which resolves the reliability issue at high frequencies
2Measurement precision
If the pre-charging period is extended to ensure reliable phase detection, then the detection accuracy improves, but the response time deteriorates
Solution Approach 1:
The patent uses feedback control through the balancer circuit, which continuously monitors the voltage levels of the phase detection outputs and dynamically adjusts them to maintain equality. This feedback mechanism ensures accurate pre-charging without requiring excessively long pre-charging periods, thus maintaining fast response time while achieving high detection accuracy
3Device complexity
If the outputs of the phase detection circuit are not equalized, then the circuit complexity remains low, but the phase detection reliability deteriorates at high frequencies
Solution Approach 1:
The patent introduces an intermediary balancer circuit that mediates between the phase detection circuit outputs and the external environment. This balancer circuit equalizes the voltage levels of both outputs without significantly increasing overall system complexity, using simple switching mechanisms controlled by the clock signals to achieve reliable high-frequency phase detection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reliable and accurate phase detection regardless of frequency, as demonstrated by simulations at 2 GHz and 3 GHz, where the outputs are consistently pre-charged to the same voltage level, improving detection accuracy.
Implementation Method 1
a balancer configured with transistors to equalize the outputs of the phase detection circuit to a substantially the same voltage level during pre-charging periods
Data Source
AI summary
Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the phase detection circuit for a phase detection. The phase detection circuit of one or more embodiments includes a cross-coupled latch configured to receive the two clock signals and generate a first latch output and a second latch output in response to the two clock signals. The aforementioned balancer is configured to substantially equalize the voltage levels of the first and second latch outputs before the phase detection circuit detects a phase difference between the two clock signals. For example, the balancer might pre-charge the outputs of the phase detection circuit to substantially the same voltage level before phase detection.