Balanced Routing Tree Generation Using Wavefront Analysis
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Solution Overview
Problem
Existing electronic design automation (EDA) systems face challenges in generating balanced routing trees for integrated circuit designs, particularly in minimizing skew and wire length while meeting timing constraints, which affects signal integrity and performance.
Innovation Solution
The approach involves using wavefront analysis to identify branch points in routing trees, applying bottom-up wavefront expansion to select branch points based on cost functions, and inserting buffers to ensure symmetry and balance, thereby optimizing routing tree structures for reduced skew and wire length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional routing methods are used to connect source to sinks, then routing can be completed, but skew and wire length cannot be minimized effectively
Solution Approach 1:
The patent segments the routing process into multiple hierarchical levels (H-tree structure), dividing the overall routing problem into smaller sub-problems that can be solved independently at each level, thereby achieving better balance and reduced skew while maintaining manageable complexity
Solution Approach 2:
The patent performs preliminary placement of buffers and determination of branch points before final routing completion. This preliminary action allows the routing structure to be pre-optimized for balance and timing, minimizing skew before the actual signal transmission is established
2Reliability
If routing tree is optimized for balance, then skew is minimized, but wire length may increase
Solution Approach 1:
The patent applies local quality by inserting buffers at specific locations within the routing tree where needed to correct timing imbalances. This allows localized adjustment of signal timing without requiring complete re-routing, thereby maintaining overall wire length efficiency while achieving better signal integrity
Solution Approach 2:
The patent changes the parameter of buffer insertion points and routing branch locations to optimize the balance between skew minimization and wire length. By adjusting these parameters iteratively, the system achieves the optimal trade-off between signal integrity and routing efficiency
3Reliability
If buffers are inserted to balance routing, then skew decreases, but device complexity increases
Solution Approach 1:
The patent implements a self-service mechanism where the routing algorithm automatically determines optimal buffer insertion points and quantities based on timing analysis, eliminating the need for manual intervention. This automation reduces the perceived complexity while ensuring timing constraints are met
Data Source
AI summary
Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design with a source and a plurality of sinks, and then using a first bottom-up wavefront analysis to select branch point candidates for the sinks. A branch point cost function is used to select among the branch point candidates. This process may be repeated until a final tier of analysis results in a final wavefront that is within a threshold distance of the source. The selected branch points are then used in generating a routing tree between the source and the sinks. In various different embodiments, different cost point functions may be used, and different operations used to manage obstructions or other specific routing considerations.