Balanced Secondary Clock Generation With Dithered Multi-Phase Division
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Solution Overview
Problem
Existing RF communication and mixed signal systems face inefficiencies in generating secondary clocks from a root clock, leading to under-utilization of clock edges and digital spurs that degrade system performance, requiring changes in the number of parallel hardware with frequency changes.
Innovation Solution
A system utilizing a dithered clock divider and multi-phase clock generator with a pseudo-random pattern to divide the primary clock into blocks of dithered clock signals, providing secondary clock signals from multiple phases with a random division ratio, ensuring balanced operation and reduced digital spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed division ratio is used to generate secondary clocks, then the clock generation is simple, but clock edges are under-utilized leading to digital spurs
Solution Approach 1:
The patent applies dynamics by making the division ratio variable rather than fixed. The system dynamically adjusts the division ratio based on the root clock frequency to ensure optimal utilization of clock edges. This is achieved through a lookup table that maps root clock frequencies to appropriate division ratios, allowing the system to adapt to different operating conditions and eliminate digital spurs without excessive complexity.
Solution Approach 2:
The patent changes the parameter of division ratio from a fixed value to a variable that depends on the root clock frequency. By modifying this key parameter based on operating conditions, the system optimizes clock edge utilization and eliminates digital spurs. The division ratio is selected from a set of predefined values based on the detected root clock frequency,实现ing parameter adaptation.
2Object-generated harmful factors
If the number of parallel hardware is increased to utilize all clock edges, then digital spurs are reduced, but hardware complexity and power consumption increase
Solution Approach 1:
Instead of increasing the number of parallel hardware components, the patent changes the division ratio parameter to optimize clock edge utilization. This parameter-based solution achieves spur reduction without proportionally increasing hardware complexity. The system selects from a set of division ratios (e.g., divide-by-2, divide-by-3, divide-by-4) based on the root clock frequency, avoiding the need for extensive parallel hardware.
Solution Approach 2:
The system dynamically selects the appropriate division ratio based on the root clock frequency rather than using a fixed hardware configuration. This dynamic adaptation allows the system to achieve optimal performance across different frequencies without requiring a fixed large number of parallel hardware components for all possible scenarios.
3Object-generated harmful factors
If the division ratio is changed to utilize all clock edges, then digital spurs are reduced, but the system must adapt when root clock frequency changes
Solution Approach 1:
The patent implements a lookup table that stores optimal division ratios for different root clock frequencies. When the root clock frequency changes, the system queries the lookup table to retrieve the appropriate division ratio, ensuring continuous optimal performance. This parameter-based adaptation mechanism maintains low digital spurs across varying frequencies without requiring complex real-time calculations or hardware reconfiguration.
Solution Approach 2:
The system incorporates feedback by monitoring the root clock frequency and automatically adjusting the division ratio based on the detected frequency. This closed-loop approach ensures that the system continuously operates with optimal parameters, adapting to frequency changes while maintaining low digital spur levels through automatic division ratio selection.
4Ease of manufacture
If fixed parallel hardware is used, then the system is simple to implement, but power consumption increases due to under-utilization of clock edges
Solution Approach 1:
The patent changes the division ratio parameter based on root clock frequency to optimize power consumption. By selecting the most appropriate division ratio from a set of predefined values, the system ensures efficient utilization of clock edges, reducing unnecessary switching activity and associated power consumption while maintaining implementation simplicity through a lookup table approach.
Solution Approach 2:
The system dynamically adjusts the division ratio to match the root clock frequency, optimizing power efficiency for different operating conditions. This dynamic parameter adjustment reduces power consumption by avoiding under-utilization of clock edges, which would otherwise cause unnecessary switching activity in the digital circuitry, while keeping the implementation relatively simple.
Data Source
AI summary
A system for generating secondary clock signals from a primary clock signal includes a dithered clock divider which has a first input adapted to receive the primary clock signal and a second input adapted to receive a random division ratio. The dithered clock divider provides a dithered clock signal. The system includes a multi-phase clock generator which has a first input adapted to receive the primary clock signal, a second input adapted to receive the dithered clock signal, and a third input adapted to receive a pseudo-random pattern. The multi-phase clock generator provides the secondary clock signals from multiple phases of the dithered clock signal. The system includes a pseuodo-random pattern generator which provides the pseudo-random pattern.