Balanced Semiconductor Package Warping
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Solution Overview
Problem
Conventional semiconductor packages experience warping due to thermal stress caused by the mismatch in thermal expansion coefficients and Young's modulus between the semiconductor chip and the insulating layers, leading to uneven physical properties on either side of the package.
Innovation Solution
A semiconductor package design where a semiconductor chip is embedded on one side and a second semiconductor chip is mounted on the opposite side, with corresponding resin layers balancing the physical properties, ensuring a well-balanced structure by forming the wiring substrate and sealing resin with similar thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a semiconductor chip is embedded only in the first insulating layer on one side of the package, then the manufacturing process is simplified, but warping occurs due to uneven physical properties between the two sides of the package
Solution Approach 1:
The patent applies asymmetry by having a semiconductor chip embedded in the first insulating layer on the first side, while placing a second semiconductor chip on the second side with a second sealing insulating layer, creating an asymmetric structure that balances physical properties between both sides of the package
Solution Approach 2:
The patent uses the second semiconductor chip and second sealing insulating layer on the second side as a counterweight to balance the first semiconductor chip and first sealing insulating layer on the first side, preventing warping by equalizing the physical properties (thermal expansion coefficient and Young's modulus) on both sides of the package
2Ease of manufacture
If the support member is removed after manufacturing, then the package structure is completed, but loss of balance in physical properties causes warping
Solution Approach 1:
The patent performs preliminary action by embedding the first semiconductor chip in the first insulating layer and placing the second semiconductor chip on the second side before removing the support member, ensuring that the physical properties are balanced in advance to prevent warping after support removal
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces warping due to thermal stress by balancing the thermal expansion coefficients and Young's modulus between the upper and lower sides of the package, maintaining structural integrity and preventing significant deformation.
Implementation Method 1
a first sealing insulating layer including a first surface positioned toward the target circuit surface and a second surface positioned opposite to the first surface, the first sealing insulating layer sealing the target circuit surface and the side surface
Implementation Method 2
the thermal expansion coefficient of the semiconductor chip is approximately 3.4 ppm/° C., and the Young's modulus of the semiconductor chip is 200 GPa. Meanwhile, in a case where an epoxy type resin is the main component of the first insulating layer or the other insulating layer, the thermal expansion coefficient of the first insulating layer or the other insulating layer is approximately 8-150 ppm/° C. and the Young's modulus of the first insulating layer or the other insulating layer is approximately 0.03-13 GPa
Implementation Method 3
the Young's modulus of the semiconductor chip is 200 GPa. Meanwhile, in a case where an epoxy type resin is the main component of the first insulating layer or the other insulating layer, the Young's modulus of the first insulating layer or the other insulating layer is approximately 0.03-13 GPa
Implementation Method 4
a wiring layer formed on the first surface of the first sealing insulating layer
Implementation Method 5
a second sealing insulating layer formed on the second surface and sealing the second semiconductor chip
Data Source
AI summary
A semiconductor package includes a first semiconductor chip including a target circuit surface and a side surface, a first sealing insulating layer including a first surface positioned toward the target circuit surface and a second surface positioned opposite to the first surface, the first sealing insulating layer sealing the target circuit surface and the side surface, a wiring layer formed on the first surface of the first sealing insulating layer, an insulating layer formed on the wiring layer, a second semiconductor chip mounted on the second surface of the first sealing insulating layer, and a second sealing insulating layer formed on the second surface and sealing the second semiconductor chip.