Balanced Transformer Winding Layout for Lower EMI Radiation
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Solution Overview
Problem
Electronic devices face electromagnetic interference (EMI) issues due to parasitic interwinding capacitance in transformers, particularly at high input voltages, leading to secondary ground bounce and EMI radiation.
Innovation Solution
A multilevel lamination structure with balanced primary and secondary transformer windings and a shield winding is used, where the windings have vertically aligned ends and are positioned between core layers and dielectric layers to mitigate EMI by balancing interwinding capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If non-symmetrical distributed interwinding capacitance is used in transformer, then device complexity is reduced, but EMI radiation increases particularly at high input voltages
Solution Approach 1:
The patent applies asymmetry principle by intentionally creating non-symmetrical distributed interwinding capacitance through asymmetric winding arrangements. The primary and secondary windings are positioned at different distances from the core, with the primary winding closer to the core than the secondary winding. This asymmetric configuration creates unequal capacitance distribution that, when properly designed, balances the overall interwinding capacitance and reduces EMI radiation while maintaining a relatively simple transformer structure.
Solution Approach 2:
The patent implements local quality by varying the capacitance characteristics at different locations within the transformer. Specifically, the interwinding capacitance is deliberately made non-uniform, with different capacitance values between primary and secondary windings at different positions. This localized variation in capacitance quality allows the transformer to achieve balanced overall capacitance and reduced EMI while maintaining structural simplicity.
2Object-generated harmful factors
If symmetrical transformer winding design is used, then EMI radiation is reduced, but device complexity increases
Solution Approach 1:
The patent resolves this contradiction by demonstrating that a controlled asymmetric design can achieve the EMI reduction benefits of symmetry without the complexity overhead. By intentionally designing asymmetric winding positions and capacitance distributions, the patent achieves balanced interwinding capacitance and reduced EMI radiation while maintaining a simpler, more practical transformer structure compared to fully symmetrical designs.
3Reliability
If parasitic interwinding capacitance is increased, then transformer coupling is improved, but secondary ground bounce increases causing EMI
Solution Approach 1:
The patent applies parameter changes by optimizing the interwinding capacitance value and distribution to achieve an optimal balance. By carefully controlling the capacitance parameters through asymmetric winding arrangements and positioning, the patent improves transformer coupling efficiency while simultaneously reducing secondary ground bounce and EMI radiation to acceptable levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces EMI radiation by balancing interwinding capacitance, providing a reliable and repeatable solution for EMI reduction in transformer-based circuits without increasing device size or requiring external circuitry.
Implementation Method 1
The injected current creates a secondary ground bounce which generates a line disturbance that is potentially coupled into another circuit or that excites power supply wires acting as an emitting antenna. Differential mode voltage of a transformer with non-symmetrical distributed interwinding capacitance contributes to EMI radiation
Implementation Method 2
Electronic devices can be a source of electromagnetic interference (EMI) and many devices are tested to EMI radiated and conducted emissions specifications
Data Source
AI summary
An electronic device includes a multilevel lamination structure having a core layer, dielectric layers and conductive features formed in metal layers on or between respective ones or pairs of the dielectric layers. The core layer and the dielectric layers extend in respective planes of orthogonal first and second directions and are stacked along an orthogonal third direction. The conductive features include a first patterned conductive feature having multiple conductive turns in each of a first pair of the metal layers to form a first winding having a first turn and a final turn adjacent to one another in the same metal layer of the first pair, and a second patterned conductive feature having multiple conductive turns in a second pair of the metal layers to form a second winding having a first turn and a final turn.