Balancer-Based Hardware Messaging for Cache-Miss Communication Load
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Solution Overview
Problem
Existing computing architectures face challenges with high latency and energy consumption due to significant data movement between processors and memory, constraining performance and capacity, particularly in systems with high cache miss rates and complex communication requests.
Innovation Solution
Implementing compute-near-memory (CNM) systems with hybrid threading processors and custom compute fabrics, utilizing network structures for efficient communication between hardware elements, and employing a balancer element to manage requests and reduce network structure load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is moved between processors and memory using conventional bus architecture, then system compatibility and simplicity are maintained, but latency increases and throughput decreases
Solution Approach 1:
The system segments the monolithic bus architecture into multiple dedicated communication paths (first data path, second data path, third data path) for different types of operations. Each path is optimized for specific traffic patterns, allowing parallel data transfers and reducing contention-induced latency.
Solution Approach 2:
The patent introduces a fourth dimension to the traditional von Neumann architecture by adding a dedicated time-multiplexed path for broadcast operations. This separates broadcast traffic from point-to-point communication, enabling simultaneous operations in different dimensional spaces and reducing overall system latency.
2Productivity
If more communication paths are added to increase throughput, then data transfer capacity improves, but device complexity increases
Solution Approach 1:
The system employs dynamic path selection where the network structure automatically routes traffic through different data paths based on operation type and current resource availability. This dynamic allocation allows the system to achieve high throughput for various operation types without requiring all paths to be simultaneously active, managing complexity through adaptive behavior.
Solution Approach 2:
The network structure is designed with multi-functional components that can handle multiple operation types across different data paths. The same routing logic and control mechanisms serve both point-to-point and broadcast operations, reducing the need for separate dedicated control structures and managing overall system complexity.
3Speed
If broadcast operations are handled through the same data path as point-to-point operations, then device complexity is reduced, but broadcast latency increases and throughput decreases
Solution Approach 1:
The system segments broadcast operations into a dedicated third data path that operates independently from point-to-point communication paths. This segmentation allows broadcast operations to proceed without interfering with or being interfered by other traffic types, achieving high-speed broadcasting while maintaining manageable complexity through specialized handling.
4Loss of time
If data is cached more aggressively to reduce memory access latency, then access speed improves, but cache miss rate increases for complex operations
Solution Approach 1:
The patent introduces a broadcast data path that operates in a separate dimensional space from traditional cache-based access patterns. This allows broadcast operations to bypass cache limitations and directly access memory or other sources, maintaining high throughput for operations that would otherwise suffer from cache misses while preserving cache effectiveness for random access patterns.
Data Source
AI summary
Various examples are directed to an arrangement comprising a first hardware compute element and a hardware balancer element. The first hardware compute element may send a first request message to a hardware balancer element. The first request message may describe a processing task. The hardware balancer element may send a second request message towards a second hardware compute element for executing the processing task and send to the first compute element a first reply message in reply to the first request message. After sending the first reply message, the hardware balancer element may receive a first completion request message indicating that the processing task is assigned and send, to the first hardware computing element, a second completion request message, the second completion request message indicating that the processing task is assigned.