Ball-Less Chip Assembly With Anisotropic Interconnects for Low Loss
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Solution Overview
Problem
Chip assemblies with ball grid arrays (BGAs) face challenges in reducing insertion loss and footprint while maintaining high IO density and power delivery, as increasing the number of solder balls increases the package size and trace length, leading to higher insertion loss.
Innovation Solution
Implementing a ball-less pad array with an anisotropic layer to electrically and mechanically couple the package substrate to the board, reducing the size of the interconnects and traces, and using a bridge device with a redistribution layer to provide signals according to different pinouts, thereby reducing the footprint and insertion loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of solder balls is increased to maintain high IO density, then the electrical connection capability is improved, but the package size and trace length increase, leading to higher insertion loss
Solution Approach 1:
The patent extracts and removes the solder balls from the interconnection structure, replacing them with a pad array directly coupled to the board. This eliminates the need for solder balls while maintaining electrical connection capability, thereby reducing trace length and insertion loss.
Solution Approach 2:
The patent transitions from a three-dimensional interconnection structure (package substrate with solder balls) to a more planar integration where pads are directly coupled to the board. This dimensional change reduces the vertical height and trace length, thereby reducing insertion loss while maintaining IO density.
2Reliability
If the number of solder balls is increased to maintain high IO density, then the electrical connection capability is improved, but the package footprint increases
Solution Approach 1:
The patent removes the solder balls from the structure, eliminating their contribution to the package footprint. The pad array directly coupled to the board occupies less space than an equivalent number of solder balls would require, thereby reducing the overall package footprint while maintaining electrical connection capability.
Solution Approach 2:
The patent merges the function of solder balls (electrical connection and mechanical support) into a single pad array structure that is directly coupled to the board. This consolidation eliminates the need for separate solder ball components, reducing the overall footprint while maintaining the same electrical connection capability.
3Reliability
If the number of solder balls is increased to maintain high IO density, then the electrical connection capability is improved, but the trace length increases, leading to higher insertion loss
Solution Approach 1:
The patent extracts and removes the solder balls, which eliminates the need for long traces to reach the solder ball locations. The pad array is positioned closer to the board, significantly reducing trace length and thereby reducing insertion loss while maintaining electrical connection capability.
Solution Approach 2:
The patent changes the spatial arrangement from a vertical three-dimensional structure (traces extending down to solder balls) to a more planar configuration where pads are directly coupled to the board. This dimensional change reduces the effective trace length in the vertical dimension, thereby reducing insertion loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a compact interconnection with reduced insertion loss and footprint, allowing for higher IO density without increasing the package substrate size, and provides a strong adhesive bond without the need for solder balls.
Implementation Method 1
an anisotropic layer positioned between the board and the one or more pads and between the board and a portion of the package substrate, the anisotropic layer mechanically coupling the board to the one or more pads and to the portion of the package substrate
Data Source
AI summary
A chip assembly may include a package substrate that includes one or more pins. The chip assembly may also include one or more pads. The one or more pads may be electrically coupled to the one or more pins. In addition, the chip assembly may include a board that includes one or more board pads. Further, the chip assembly may include an anisotropic layer. The anisotropic layer may be positioned between the board and the one or more pads and between the board and a portion of the package substrate. In addition, the anisotropic layer may mechanically couple the board to the one or more pads and to the portion of the package substrate. Further, the anisotropic layer may electrically couple the one or more pads to the one or more board pads.