Ballast Resistor Mitigates Single Event Latch-Up in CMOS
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Solution Overview
Problem
Single event latch-up (SEL) in integrated circuits leads to abnormal high-current states, causing device functionality loss and potential damage due to continuous current conduction, which existing technologies fail to mitigate effectively without power cycles or guard rings.
Innovation Solution
Implementing ballast resistors in series with parasitic silicon controlled rectifier (SCR) structures between power and ground nodes, causing a voltage drop that prevents continuous current conduction and turns off the parasitic SCR without a power cycle or guard ring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional CMOS structures are used without additional mitigation components, then device complexity is low, but the device is vulnerable to SEL causing continuous current conduction and potential damage
Solution Approach 1:
The patent introduces a ballast resistor as an intermediary component connected in series with the power supply to the parasitic SCR structure. This resistor limits the current flowing through the SCR during latch-up events, preventing the harmful high-current state from causing damage. The ballast resistor acts as a mediator that controls the electrical interaction between the power supply and the parasitic SCR, enabling SEL mitigation without requiring complex circuit reconfiguration or additional active components.
2Reliability
If guard rings are implemented to mitigate SEL, then reliability improves, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent extracts the SEL mitigation function from the traditional guard ring approach and implements it through a separate ballast resistor component. Instead of modifying the semiconductor substrate structure with complex guard ring patterns during manufacturing, the solution moves the mitigation functionality to an external or integrated resistor element that can be added through simpler processes. This separation of concerns allows standard CMOS manufacturing to be used while still providing SEL protection.
3Object-generated harmful factors
If power cycling is used to turn off parasitic SCR after SEL, then current conduction can be stopped, but device operation is interrupted and productivity is reduced
Solution Approach 1:
The patent implements preliminary action by pre-configuring the ballast resistor in series with the power supply before any latch-up event occurs. This resistor is already in place and properly sized to limit current during potential SEL events. When latch-up occurs, the current limitation effect is immediately active without requiring any reactive measures like power cycling. The preliminary configuration of the ballast resistor ensures continuous device operation while providing automatic protection against harmful current conduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively mitigates SEL by preventing the parasitic SCR from reaching hold voltage, thereby stopping current conduction and avoiding damage without the need for power cycles or guard rings, enhancing the reliability of integrated circuits.
Implementation Method 1
the ballast resistor can cause a parasitic SCR structure to turn off after occurrence of the SEL without a power cycle... The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node
Data Source
AI summary
Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.