Ballistic Transistor Source Drain Contact Geometry
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Solution Overview
Problem
As semiconductor devices scale down, source/drain (S/D) resistance (RSD) becomes a critical parameter affecting current drivability, especially due to the presence of ballistic and quasi-ballistic carriers, which conventional classical resistance models fail to accurately address, particularly in extremely scaled CMOS devices with novel channel materials.
Innovation Solution
Geometrical designs and fabrication processes for S/D epitaxial regions and metal contacts are implemented to reduce RSD, including 'raised', 'angled', and 'edge' S/D architectures, which optimize carrier injection, collection, and contact area to manage ballistic and quasi-ballistic carriers, thereby reducing RSD and enhancing current drivability without the need for higher S/D doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device scaling is continued to improve integration density, then productivity increases, but source/drain resistance becomes increasingly problematic affecting current drivability
Solution Approach 1:
The patent transitions from planar 2D contact geometry to 3D vertical contact structures. The raised source/drain regions extend upward from the substrate, creating vertical contact interfaces that increase the effective contact area without increasing the lateral device footprint. This dimensional change allows continued scaling while maintaining adequate current drivability through enhanced contact geometry.
Solution Approach 2:
The patent implements nested contact structures where metal contacts are positioned within or adjacent to the raised source/drain regions. The contact structure is embedded within the vertical profile of the device, with the metal contact nested against the vertical sidewalls and top surface of the raised source/drain region, maximizing space utilization and contact area in a compact configuration.
2Reliability
If source/drain doping is increased to reduce resistance, then electrical conductivity improves, but manufacturing complexity and doping challenges in small devices increase
Solution Approach 1:
The patent changes the geometric parameters of the source/drain contact region by raising them vertically from the substrate plane. This parameter change transforms the contact from a planar interface to a three-dimensional structure with increased surface area, thereby improving electrical conductivity through enhanced contact area rather than relying solely on increased doping concentration. This approach avoids the manufacturing complexities associated with high-dose doping in scaled devices.
Data Source
AI summary
An embodiment includes an apparatus comprising: a transistor including an epitaxial source, a channel, and an epitaxial drain; a fin that includes the channel, the channel including a long axis and a short axis; a source contact corresponding to the source; and a drain contact corresponding to the drain; wherein (a) an additional axis intersects each of the source contact, the source, the drain, and the drain contact, and (b) the additional axis is parallel to the long axis. Other embodiments are described herein.