Balun Ground Path Layout for Higher Loaded-Q

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Solution Overview

Problem

The quality factor (Q) of baluns coupled to subsequent loading stages is reduced due to resistive load elements, leading to poorer performance in communications devices, as parasitic inductances in the ground path decrease the balun output voltage and signal-to-noise ratio (SNR).

Innovation Solution

Coupling the balun secondary element to the amplifier source node via a common ground node, with the common ground node connected to a ground voltage, and using a peaking inductor to minimize parasitic inductances and enhance the balun output voltage, while maintaining a short connection length to reduce series resistive components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the balun secondary element is coupled to subsequent loading stages with resistive load elements, then the balun can drive the loading stages, but the quality factor (loaded-Q) of the balun is reduced

Engineering Contradiction:
Improvebalun output voltageVSAvoidquality factor (loaded-Q)
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent introduces a common ground node as an intermediary between the balun secondary element and the amplifier source node. This ground node serves as a mediator that provides a low-impedance return path, isolating the balun from the resistive loading effects while maintaining proper signal coupling. The ground node acts as a buffer that prevents direct interaction between the balun's high-Q resonant circuit and the amplifier's resistive input.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts the ground connection from the traditional signal path and creates a separate, dedicated ground return path through the common ground node. By taking out the ground reference and making it explicit, the design separates the signal coupling function from the ground reference function, allowing the balun to maintain its resonant Q while still driving the amplifier.

Inventive Principle:
Principle #2Taking out (Extraction)

2Ease of manufacture

If parasitic inductances in the ground path are present, then the circuit can be implemented with standard layout, but the balun output voltage and signal-to-noise ratio are decreased

Engineering Contradiction:
Improvecircuit implementationVSAvoidparasitic inductances
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by creating a low-inductance ground path specifically at the critical interface between the balun and amplifier. The common ground node is positioned and connected with minimal trace length to locally minimize parasitic inductance where it matters most, while other parts of the circuit can use standard layout practices. This localized optimization reduces the harmful effects of parasitic inductance without requiring complete redesign of the entire circuit layout.

Inventive Principle:
Principle #3Local quality

3Ease of operation

If the connection length between balun secondary element and amplifier is increased, then the circuit layout is simplified, but series resistive components increase and performance deteriorates

Engineering Contradiction:
Improvecircuit layoutVSAvoidconnection length control
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The patent creates an equipotential ground reference at the common ground node, ensuring that both the balun secondary element and amplifier source node share the same ground potential. This equipotential connection minimizes voltage drops and resistive losses even when physical connection lengths vary, allowing for more flexible circuit layout without compromising performance. The ground node acts as a common reference that equalizes the potential across the interface.

Inventive Principle:
Principle #12Equipotentiality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach increases the quality factor of the balun, enhancing the balun output voltage and resonance frequency, thereby improving the overall device performance by minimizing parasitic inductances and maintaining stability.

Implementation Method 1

using a peaking inductor to minimize parasitic inductances and enhance the balun output voltage

Methodology Applied
Scientific EffectInductance: Inductor

Implementation Method 2

A common balun implementation includes two mutually coupled inductive elements, configured such that a differential voltage across the first (primary) balun element generates a corresponding single-ended voltage across the second (secondary) balun element

Methodology Applied
Scientific EffectElectromagnetic induction: Electromagnetic Induction

Data Source

PatentUS7863986B2Techniques for improving balun loaded-Q
Publication Date: 2011.01.04 QUALCOMM INC
  • US7863986B2 patent drawing
  • US7863986B2 patent drawing
  • US7863986B2 patent drawing

AI summary

Techniques for improving the quality factor (“Q”) of a balun in the presence of loading stages are disclosed. In an exemplary embodiment, the ground node of a balun secondary (single-ended) element is connected to a source node of an amplifier stage via a common ground node. The connection may be made physically short to minimize any parasitic elements. In another exemplary embodiment, the common ground node may be coupled to an off-chip ground voltage via a peaking inductor. The peaking inductor may be implemented on-chip, e.g., as a spiral inductor, or off-chip e.g., using bondwires.