Band Edge Gate Metals as Source Drain Contacts
Solution Overview
Problem
Contact resistance in transistor devices, particularly in CMOS transistors, becomes a significant challenge as devices are scaled to smaller dimensions, necessitating a reduction in source/drain contact resistance while maintaining compatibility with existing processes and being cost-effective.
Innovation Solution
The use of band edge gate metals as source/drain contacts, which eliminates the need for silicide formation and simplifies the process flow by directly depositing gate metals over doped semiconductor regions, reducing Schottky barrier height and contact resistance through physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact structures are used in scaled transistor devices, then existing processes can be maintained, but contact resistance becomes dominating and degrades device performance
Solution Approach 1:
The patent merges the gate metal layer and source/drain contact structure into a single integrated formation process. The gate metal is deposited continuously across the gate region and source/drain contact regions, eliminating the need for separate silicide formation and contact metallization steps. This merging of structures directly reduces contact resistance while maintaining process simplicity.
Solution Approach 2:
The gate metal layer serves multiple functions simultaneously: it forms the gate electrode over the gate dielectric, and it forms the source/drain contact electrodes over the doped semiconductor regions. This multi-functionality eliminates the need for separate contact materials and reduces the number of process steps, thereby improving contact resistance without increasing device complexity.
2Reliability
If silicide formation is used to reduce contact resistance, then contact resistance decreases, but process complexity increases and metal diffusion is minimized only with additional steps
Solution Approach 1:
The patent extracts and eliminates the silicide formation step from the conventional contact fabrication process. By using gate metals with appropriate work functions that directly contact the doped semiconductor, the need for intermediate silicide layers is removed. This extraction simplifies the manufacturing process while maintaining low contact resistance through proper metal selection.
Solution Approach 2:
The patent changes the key parameter of contact resistance reduction from relying on silicide formation to relying on work function matching between the gate metal and semiconductor. By selecting gate metals with work functions optimized for the semiconductor band structure, low contact resistance is achieved directly without silicide, simplifying the manufacturing process.
3Reliability
If gate metals are deposited directly over doped regions, then contact resistance is reduced and process flow is simplified, but metal diffusion control becomes critical
Solution Approach 1:
The gate dielectric layer serves as an intermediary that prevents metal diffusion into the semiconductor substrate in the gate region, while allowing the gate metal to directly contact the doped source/drain regions where diffusion control is less critical. This intermediary structure enables direct contact for low resistance while maintaining diffusion barriers where needed.
Solution Approach 2:
The patent applies different functional requirements to different regions: in the gate region, the metal is isolated by gate dielectric to prevent diffusion, while in the source/drain contact regions, the metal directly contacts the doped semiconductor for low resistance. This local differentiation of quality allows simultaneous achievement of diffusion control and low contact resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces source/drain contact resistance, eliminates the need for silicide formation, and improves yield by minimizing metal diffusion, thereby enhancing the performance and reliability of CMOS transistors.
Implementation Method 1
reducing Schottky barrier height and contact resistance through physical vapor deposition, chemical vapor deposition, or atomic layer deposition
Implementation Method 2
reducing Schottky barrier height and contact resistance through physical vapor deposition, chemical vapor deposition, or atomic layer deposition
Implementation Method 3
reducing Schottky barrier height and contact resistance through physical vapor deposition, chemical vapor deposition, or atomic layer deposition
Implementation Method 4
reducing Schottky barrier height and contact resistance through physical vapor deposition, chemical vapor deposition, or atomic layer deposition
Data Source
AI summary
A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.