Band-Engineered Memory Cell for Low Voltage Operation
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Solution Overview
Problem
Current Flash/EEPROM and SONOS memory devices face challenges with voltage scalability, high power consumption, slow write and erase speeds, and limited device endurance due to high programming voltages, which hinder feature size scaling and memory density.
Innovation Solution
A band-engineered non-volatile memory cell with multiple trapping sites and layers, featuring a substrate with implanted regions, a multiple layer tunnel dielectric, and a composite trapping layer that allows low voltage programming and erasure, enhancing charge retention and speed through band-engineered tunnel and charge blocking layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high programming voltage is used for Flash/EEPROM/SONOS memory cells, then programming and erasure can be achieved, but device endurance and retention are damaged due to material damage and generated flaws
Solution Approach 1:
The patent changes the voltage parameter from high voltage to low voltage operation by engineering the band structure of the insulator layers. The asymmetric band alignment allows efficient charge injection at low voltages while preventing the material damage caused by high voltage stress, thus improving device endurance and retention
Solution Approach 2:
The patent uses a composite insulator structure with multiple layers having different band offsets (e.g., SiO2/Si3N4/SiO2). This composite structure enables low voltage operation through optimized band alignment while maintaining effective charge trapping, resolving the contradiction between programming capability and device reliability
2Quantity of substance
If feature size is scaled down to increase memory density, then memory density improves, but voltage scalability is affected and neighboring cells are disturbed by capacitive coupling during programming
Solution Approach 1:
The patent changes the voltage parameter to low voltage operation, which reduces the capacitive coupling effect during programming. This allows feature size scaling to proceed without the neighboring cell disturbance problem that plagues high voltage memory devices, enabling continued improvement in memory density
3Productivity
If high programming voltage is used, then charge can be injected into trapping layers, but write and erase speeds remain slow in the order of milliseconds
Solution Approach 1:
The patent changes the voltage parameter to low voltage operation combined with optimized band alignment in the insulator layers. This enables efficient charge injection through quantum tunneling mechanisms at low voltages, achieving fast write and erase speeds while maintaining effective charge trapping capability
4Productivity
If high programming voltage and current are used, then programming operations can be performed, but power consumption is relatively high requiring external or on-chip high voltage/current supplies
Solution Approach 1:
The patent changes the voltage parameter to low voltage operation through band engineering of the insulator layers. This eliminates the need for high voltage/current supplies and significantly reduces power consumption while maintaining effective programming operation capability through optimized charge injection mechanisms
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables low voltage, high-speed programming and erasure, improves charge retention, and extends device lifespan, allowing for increased memory density and scalability while reducing material damage, effectively addressing the limitations of existing technologies.
Implementation Method 1
the band-engineered tunnel layer is adapted to allow low voltage Fowler-Nordheim or direct tunneling injection of electrons from the channel region to the composite charge trapping layer
Implementation Method 2
the band-engineered tunnel layer is adapted to allow low voltage Fowler-Nordheim or direct tunneling injection of electrons from the channel region to the composite charge trapping layer
Implementation Method 3
the band-engineered charge blocking layer is adapted to allow low voltage Fowler-Nordheim or direct tunneling injection of holes from the control gate to the composite trapping layer
Implementation Method 4
the band-engineered charge blocking layer is adapted to allow low voltage Fowler-Nordheim or direct tunneling injection of holes from the control gate to the composite trapping layer
Data Source
AI summary
Non-volatile memory devices and arrays are described that utilize band engineered gate-stacks and multiple charge trapping layers allowing a multiple trapping site gate-insulator stack memory cell that utilizes a band engineered direct tunneling or crested barrier tunnel layer and charge blocking layer for high speed programming/erasure. Charge retention is enhanced by utilization of nano-crystals and/or bulk trapping materials in a composite non-conductive trapping layer and a high K dielectric insulating layers. The band-gap engineered gate-stack with asymmetric direct tunneling or crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage high speed tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. Memory cell embodiments of the present invention allow multiple levels of bit storage in a memory cell through multiple charge centroids and/or multiple threshold voltage levels.