Band Gap Circuit Offset Voltage Error Correction
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Solution Overview
Problem
Conventional methods for correcting offset voltage errors in band gap circuits, such as auto-zero, offset-nulling, chopping, and high-end laser trimming, are either area-intensive, generate output glitches, or only provide temporary corrections, failing to maintain accuracy over time and across varying temperature and power supply conditions.
Innovation Solution
A band gap circuit with a diode junction circuit, error amplifier, current device, bias current generator, calibration circuit, and mode control circuit, which includes a trimming DAC and successive approximation algorithm to adjust trim currents and minimize offset voltage errors during calibration modes, ensuring accurate band gap voltage maintenance across temperature and power supply variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If auto-zero technique is used to correct offset voltage error, then accuracy is improved, but capacitor size must be very large resulting in significant area penalty
Solution Approach 1:
The patent implements periodic calibration cycles where the error amplifier is temporarily taken out of the closed-loop configuration. During these periodic calibration periods, the amplifier inputs are shorted together and the offset voltage is measured and corrected using a trim DAC. This periodic action allows high accuracy to be achieved without requiring large capacitors, as the offset correction is performed in discrete calibration bursts rather than continuously, thus avoiding the area penalty of large auto-zero capacitors.
2Measurement precision
If offset-nulling technique is used to correct offset voltage error, then accuracy is improved, but an extra pin is required on the IC
Solution Approach 1:
The patent extracts the offset correction function from the main signal path by implementing a separate calibration mode. During calibration, the error amplifier is taken out of the closed-loop configuration and its inputs are shorted together. The offset voltage is then measured and corrected through a trim DAC that applies a compensating voltage to the amplifier inputs. This extraction approach achieves high accuracy without requiring external pins, as the correction is performed internally during calibration cycles.
3Measurement precision
If chopping technique is used to correct offset voltage error, then accuracy is improved, but output glitches are generated requiring large output filter capacitor
Solution Approach 1:
The patent uses periodic calibration cycles instead of continuous chopping. During calibration mode, the error amplifier is temporarily removed from the closed-loop configuration and its inputs are shorted together to measure and correct the offset voltage using a trim DAC. This periodic approach achieves offset correction without generating continuous output glitches, thereby eliminating the need for large output filter capacitors and reducing the overall circuit area.
4Measurement precision
If laser trimming technique is used to correct offset voltage error, then accuracy is improved, but it only provides one-time permanent trim that does not correct for offset variations over time
Solution Approach 1:
The patent implements continuous offset correction through periodic calibration cycles. Rather than a one-time laser trim, the system continuously monitors and corrects offset voltage variations by periodically taking the error amplifier out of closed-loop mode, measuring the offset, and applying corrections via a trim DAC. This continuous calibration approach maintains high accuracy over time and across varying temperature and power supply conditions, ensuring long-term reliability.
Data Source
AI summary
A band gap circuit with offset voltage error correction including a diode junction circuit, an error amplifier, a current device, a bias current generator, a calibration circuit, and a mode control circuit. During a normal mode of operation, the error amplifier monitors feedback nodes of the diode junction circuit and drives the current device to provide a control current to the diode junction circuit. During a calibration mode, the current device is decoupled from the diode junction circuit and the inputs of the error amplifier are shorted together, the bias generator circuit sinks a bias current from the current device and separately sources a bias current to the diode junction circuit such that the error amplifier operates as a comparator, and the calibration circuit monitors the output of the current device while adjusting a trim current of the error amplifier to minimize an offset voltage error of the error amplifier.