Band-offset semiconductor drain spacer for asymmetric FETs
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Solution Overview
Problem
High mobility semiconductor materials like III-V compound semiconductors exhibit higher off-state leakage currents due to Gate Induced Drain Leakage (GIDL) compared to silicon-based FETs, which hinders the extension of Moore's law and increases transistor density challenges.
Innovation Solution
Incorporating a wide band gap semiconductor spacer with a charge carrier-blocking band offset between the channel and drain regions to reduce band-to-band tunneling and GIDL current, while maintaining minimal impact on on-state performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high mobility semiconductor materials (III-V compound semiconductors) are used in FETs, then carrier mobility and transistor speed are improved, but off-state leakage current increases significantly due to GIDL
Solution Approach 1:
The drain region is segmented into two distinct parts: a first drain region adjacent to the channel region with high carrier mobility, and a second drain region adjacent to the first drain region with lower carrier mobility. This segmentation allows the high mobility material to provide fast carrier transport while the lower mobility material reduces GIDL current generation at the drain-gate interface.
Solution Approach 2:
Different regions of the drain are assigned different material properties tailored to their specific functions. The first drain region uses high mobility III-V material optimized for carrier injection into the channel, while the second drain region uses lower mobility material optimized for reducing off-state leakage. This local differentiation resolves the contradiction between speed and leakage.
2Productivity
If the effective channel length is reduced to increase transistor density, then device scaling is improved, but off-state leakage current increases due to higher electric fields
Solution Approach 1:
The drain structure implements spatially varying material properties where the second drain region with lower mobility is positioned specifically at the location where GIDL current is generated (adjacent to the gate). This localized property differentiation allows aggressive channel length scaling for high density while the strategically placed lower mobility region suppresses the field-induced leakage.
Solution Approach 2:
The second drain region acts as an intermediary layer between the high mobility first drain region and the gate structure. This intermediate region with lower carrier mobility serves as a buffer that reduces the electric field strength at the critical drain-gate interface, thereby suppressing GIDL current while allowing the high mobility region to maintain fast carrier transport.
3Object-generated harmful factors
If band-to-band tunneling is reduced to lower GIDL current, then off-state leakage is improved, but on-state current may be affected
Solution Approach 1:
The drain is divided into two functional segments that perform opposing functions: the first drain region with high mobility maximizes on-state current by facilitating rapid carrier injection, while the second drain region with lower mobility minimizes off-state leakage by reducing band-to-band tunneling. This segmentation allows both requirements to be satisfied simultaneously in different spatial locations.
Solution Approach 2:
Different regions are optimized for different functions: the first drain region is optimized for high current drive capability with high mobility material, while the second drain region is optimized for low leakage with lower mobility material. This local quality differentiation resolves the contradiction between on-state performance and off-state leakage suppression.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces off-state leakage current, enabling further lateral scaling and greater transistor density without worsening on-state resistance, thus supporting the extension of Moore's law.
Implementation Method 1
a band-offset semiconductor drain spacer... having a charge carrier-blocking band offset from the channel semiconductor material
Implementation Method 2
band-to-band tunneling between the drain and gate insulator may cause Gate Induced Drain Leakage (GIDL) current
Data Source
AI summary
An embodiment includes a field effect transistor, comprising: a source region comprising a first III-V material doped to a first conductivity type; a drain region comprising a second III-V material doped to a second conductivity type that is opposite the first conductivity type; a gate electrode disposed over a channel region comprising a third III-V material; and a first spacer, between the channel and drain regions, comprising a fourth III-V material having a charge carrier-blocking band offset from the third III-V material. Other embodiments are described herein.