Band-Offset Semiconductor Spacer for GIDL Reduction
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Solution Overview
Problem
High mobility field effect transistors employing III-V compound semiconductor materials face significant off-state leakage due to Gate Induced Drain Leakage (GIDL) current, which hinders the extension of Moore's law and increases transistor density limitations.
Innovation Solution
Incorporating a wide band gap semiconductor spacer with a charge carrier-blocking band offset between the channel region and the source/drain regions to reduce band-to-band tunneling and GIDL current, while maintaining minimal impact on on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high mobility III-V compound semiconductor materials are employed in the channel region, then carrier mobility is improved, but off-state leakage current increases due to GIDL
Solution Approach 1:
A wide band gap semiconductor spacer material is introduced as an intermediary layer between the high mobility III-V channel material and the source/drain regions. This spacer material has a wider band gap than the channel material, creating a band offset that acts as a barrier to carrier tunneling. The spacer is positioned in the gate-drain overlap region where the electric field is strongest, effectively blocking the tunneling path without interfering with the channel's high mobility transport when the device is on.
Solution Approach 2:
The semiconductor spacer is selectively placed only in specific regions where it is most needed - the gate-drain overlap area and potentially gate-source overlap area - rather than throughout the entire device. This localized application allows the high mobility channel material to maintain its excellent transport properties in the channel region while the spacer provides leakage suppression only where the electric field-induced tunneling occurs. The spacer thickness and position are carefully controlled to achieve the right balance between leakage reduction and on-state performance.
2Productivity
If the channel length is reduced to increase transistor density, then device scaling is improved, but off-state leakage current increases due to higher electric fields
Solution Approach 1:
The wide band gap semiconductor spacer serves as a mediator that allows further scaling of the effective channel length without proportionally increasing the GIDL current. By placing the spacer in the gate-drain overlap region, it provides an additional tunneling barrier that compensates for the reduced channel length. This enables continued transistor density improvement while the spacer maintains acceptable off-state leakage levels despite the higher electric fields associated with shorter channels.
3Object-generated harmful factors
If a wide band gap semiconductor spacer is introduced to reduce GIDL current, then off-state leakage is reduced, but device structure becomes more complex
Solution Approach 1:
The semiconductor spacer formation is merged with the existing source/drain region fabrication process. The spacer material is deposited and patterned together with the source/drain regions in a single process sequence, rather than as a separate additional step. This integration reduces the overall device structure complexity and manufacturing complexity, as the spacer and source/drain regions form a unified structure that can be processed simultaneously.
Solution Approach 2:
The wide band gap semiconductor spacer is formed preliminarily before the source/drain regions are fully created or activated. By establishing the spacer structure first in the gate-drain overlap region, the subsequent source/drain formation process can proceed without additional complexity, as the spacer is already in place to provide the necessary tunneling barrier. This preliminary action simplifies the overall device architecture by pre-positioning the leakage suppression element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The wide band gap spacer effectively reduces off-state leakage current, enabling further lateral scaling and increased transistor density without worsening on-state performance.
Implementation Method 1
a first semiconductor spacer disposed between the semiconductor channel region and at least the semiconductor drain region, the first semiconductor spacer comprising a third III-V semiconductor material having a charge carrier-blocking band offset from the first III-V semiconductor material
Data Source
AI summary
Monolithic FETs including a channel region in a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a channel region, a semiconductor spacer of a semiconductor material with a band offset relative to the channel material is grown, for example on at least a drain end of the channel region to introduce at least one charge carrier-blocking band offset between the channel semiconductor and a drain region of a third III-V semiconductor material. In some N-type transistor embodiments, the carrier-blocking band offset is a conduction band offset of at least 0.1 eV. A wider band gap and/or a blocking conduction band offset may contribute to reduced gate induced drain leakage (GIDL). Source/drain regions couple electrically to the channel region through the semiconductor spacer, which may be substantially undoped (i.e. intrinsic) or doped. In some embodiments, the semiconductor spacer growth is integrated into a gate-last, source/drain regrowth finFET fabrication process.