Band-Selection DSP Circuit for High-Rate Multi-Channel Reception
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Solution Overview
Problem
Digital signal processing systems face limitations in high sample rates due to rounding errors and increased power consumption, especially when trying to capture entire transmission bands in radio frequency receivers, leading to high circuit costs and power consumption.
Innovation Solution
A digital signal processing circuit that reduces computations by using cyclically changing combination patterns in FIR filters for band selection, allowing simultaneous digital reception of multiple channels and overlapping sub-bands to simplify channel decoding at the edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If digital signal processing is performed at very high sample rates to capture the entire transmission band, then the sampling frequency increases to capture all receivable channels, but the power consumption and circuit cost increase significantly
Solution Approach 1:
The transmission band is divided into multiple sub-bands, and processing is performed separately on each sub-band at a reduced sample rate. The overall sampling frequency is segmented into lower frequency components that can be processed more efficiently, reducing the power consumption while maintaining the ability to capture the entire transmission band through time-multiplexed processing.
Solution Approach 2:
The system dynamically switches between processing different sub-bands at reduced sample rates rather than continuously processing the entire band at high sample rate. This dynamic time-multiplexed approach allows the processor to operate at lower power consumption levels while still capturing all channels across the transmission band over time.
2Speed
If digital signal processing is performed at very high sample rates to capture the entire transmission band, then the sampling frequency increases to capture all receivable channels, but the circuit cost increases
Solution Approach 1:
The high sample rate processing is segmented into multiple lower sample rate processing stages, each handling a specific sub-band. This segmentation allows the use of simpler, lower-cost digital signal processing circuits that operate at reduced frequencies, thereby reducing overall circuit cost while maintaining the capability to process the entire transmission band through time-multiplexed operation.
Solution Approach 2:
The system uses dynamic switching between different processing configurations for different sub-bands, allowing simpler circuits to handle specific frequency ranges at reduced sample rates. This dynamic sub-band processing reduces the complexity and cost of the overall circuit compared to a single high-sample-rate processing path.
3Use of energy by moving object
If a single programmable signal processor is used to perform different parts of the processing operation in time multiplexed way at low sample rate, then power consumption is reduced, but the maximum sample rate is increasingly limited as the processing operation becomes more complex
Solution Approach 1:
The processing operation is segmented into distinct sub-band processing stages, each operating at optimized sample rates. By dividing the complex processing into smaller, specialized segments rather than attempting to process everything at once, the system achieves better power efficiency while maintaining higher effective throughput through the segmented processing pipeline.
Solution Approach 2:
The system dynamically allocates processing resources to different sub-bands based on current requirements, allowing the programmable signal processor to operate efficiently at lower power consumption levels while still achieving high maximum sample rates through intelligent time-multiplexed scheduling of processing tasks across different frequency bands.
Data Source
Figure 1~3
Figure 3a~5
AI summary
A digital signal processing circuit comprises a band selector (14) for selecting at least one sub-band from a frequency spectrum of a digital sampled input signal. The band selector (14) comprises a plurality of processing branches corresponding to respective phases and an adder (28a, 28b) for adding branch signals from the branches. Each branch comprises a sub-sampler (20a,b) for sub-sampling sample values of the input signal at the phase corresponding to the branch, a filter (24a,b) with a first FIR filter (32, 34), applied alternatingly to sets of even and to sets of odd samples from the subsampler (20a,b) and a second FIR filter (36, 38) applied to further sets of odd and even samples from the subsampler (20a,b) when the first FIR filter is applied to the even and odd sets respectively. Output samples from the first and second FIR filter (24a,b) are combined to form the branch signals of the branch, according to a changing combination pattern that changes cyclically as a function of sample position and depends on a phase for which the branch is used.