Band-Structure Engineered Diodes for High-Density Memory
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Solution Overview
Problem
Existing non-volatile memory technologies are bulky and power-consuming, limiting the battery life and size of portable devices, and conventional silicon-based diodes have limitations in bandgap, generation and recombination rates, and high-field properties.
Innovation Solution
The development of cross-point memory cells using band-structure engineered diodes with stacked thin dielectric films, which allow for vertical stacking to reduce real estate consumption and improve integration, and the use of low-temperature deposition processes to avoid thermally-induced damage, incorporating materials like Ge2Se2Te5 and metal oxides for high-density, low-cost, and high-performance memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional silicon-based diodes are used, then manufacturing compatibility is maintained, but bandgap, generation and recombination rates, and high-field properties are limited
Solution Approach 1:
The patent employs composite material structures consisting of multiple semiconductor layers with different bandgaps (e.g., wide-bandgap materials like SiC or GaN combined with conventional silicon). This composite approach enables tailored bandgap engineering to achieve desired electrical characteristics while maintaining compatibility with existing manufacturing processes.
Solution Approach 2:
The invention changes fundamental material parameters by selecting semiconductor materials with specific bandgap values, electron mobility, and breakdown characteristics. By adjusting material composition and layer thicknesses, the diode's electrical properties are optimized for high-voltage, high-temperature, or high-frequency applications.
2Area of stationary object
If vertical stacking of memory cells is implemented, then real estate consumption is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar (2D) memory cell arrangement to vertical (3D) stacking, thereby utilizing the third dimension to increase storage density. Multiple memory cells are stacked along the vertical axis, sharing common bitlines and wordlines, which reduces the footprint area while maintaining manufacturing feasibility through adapted fabrication processes.
Solution Approach 2:
The invention implements a nested structure where multiple memory cell layers are integrated vertically, with each layer containing complete memory cell functionality. The stacked cells share common conductive structures, creating a compact nested arrangement that maximizes space utilization.
3Object-affected harmful factors
If low-temperature deposition processes are used, then thermally-induced damage is avoided, but deposition precision may be compromised
Solution Approach 1:
The patent replaces thermal energy-driven deposition with alternative mechanisms such as physical vapor deposition (PVD), chemical vapor deposition (CVD) at reduced temperatures, or atomic layer deposition (ALD). These methods enable precise film formation at lower temperatures by controlling deposition through chemical reactions or physical processes rather than relying solely on thermal diffusion.
Solution Approach 2:
The invention changes the deposition process parameters by lowering temperature while compensating through extended deposition time, adjusted pressure conditions, or modified gas flow rates. This parameter optimization maintains film quality and precision without causing thermal damage to temperature-sensitive materials or underlying structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the creation of high-density, low-power, and cost-effective non-volatile memory that extends battery life and reduces device size by efficiently utilizing semiconductor real estate and avoiding high-temperature processing, while providing fast switching and high reliability.
Implementation Method 1
The diodes may contain stacked thin dielectric films, with the dielectric films being band-structure engineered to achieve tailored diode properties for particular memory cells
Implementation Method 2
The memory element may comprise Ge2Se2Te5 or other materials that exhibit two different stable stoichiometric states with different resistive states
Data Source
AI summary
Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.