Bandgap Reference Compensation Circuit for Curvature and Drift Control
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Solution Overview
Problem
Current bandgap voltage reference circuits are sensitive to MOS process corners and temperature variations, leading to inaccuracies in output voltage due to non-linearity introduced by compensation currents, which affect the curvature compensation and temperature drift behavior.
Innovation Solution
An improved compensation circuit with a CTAT linearization scheme is introduced, reducing the sensitivity to MOS process corners and temperature variations by using an operational amplifier configuration that includes specific resistor and diode connections to control the curvature of the bandgap reference voltage output, ensuring higher accuracy and reduced temperature drift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a compensation circuit is added to improve temperature independence, then temperature drift is reduced, but non-linearity is introduced due to compensation current effects
Solution Approach 1:
The patent introduces an intermediate compensation current path that mediates between the temperature compensation requirement and the non-linearity problem. By routing compensation current through a dedicated path with controlled impedance and using it to adjust the reference voltage indirectly, the circuit achieves temperature compensation while minimizing direct non-linear effects on the output.
Solution Approach 2:
The patent dynamically changes the compensation current parameter based on temperature conditions. By adjusting the magnitude and distribution of compensation current through temperature-dependent circuit elements, the system optimizes temperature drift compensation while maintaining output voltage linearity across different operating conditions.
2Stability of the object's composition
If compensation current is increased to improve temperature stability, then temperature independence improves, but sensitivity to MOS process corners increases
Solution Approach 1:
The patent segments the compensation current into multiple independent paths, each with different characteristics. This segmentation allows the circuit to achieve temperature compensation through the combined effect of multiple current paths while reducing sensitivity to variations in any single MOS device, as the overall compensation effect is distributed across multiple elements.
Solution Approach 2:
The compensation current circuit is designed to serve multiple functions simultaneously: temperature compensation, linearity improvement, and process variation mitigation. By making the compensation network multi-functional, the patent achieves temperature independence while the same circuit structures also provide immunity to MOS process corner variations.
3Temperature
If complex compensation circuits are used to reduce curvature, then temperature drift decreases, but circuit complexity increases
Solution Approach 1:
The patent merges the curvature compensation function with the existing temperature compensation circuitry. By combining multiple compensation objectives into a unified circuit architecture, the patent achieves effective curvature reduction and temperature drift compensation without proportionally increasing circuit complexity, as shared circuit elements serve multiple purposes.
Solution Approach 2:
The patent implements partial compensation through selectively activated circuit paths. By using switches or temperature-dependent elements to enable compensation only when and where needed, the circuit achieves effective curvature compensation while keeping the overall complexity manageable through conditional operation rather than always-active complex circuitry.
Data Source
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AI summary
Embodiments herein disclose a compensation circuit including an OPAMP having an input connected to a node between one end of a first resistor and a drain of a first PMOS. A fifth PMOS includes a drain connected to a drain of a second NMOS and a gate of sixth PMOS. A gate of second NMOS is connected to a node between a drain of fourth PMOS and one end of third resistor. The sixth PMOS includes a drain connected to one end of fifth resistor and another end of fifth resistor connected to a node between a gate of third NMOS and a gate of a fourth NMOS. A seventh PMOS includes a drain connected to a node between another end of the second resistor and third diode.