Bandgap Reference Voltage Generator Using Folded Amplifier
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing bandgap reference voltage circuits require high power supply voltages and occupy significant silicon area due to the use of large resistors and cascoded current mirrors, which limits their efficiency and scalability.
Innovation Solution
A method and device for generating an adjustable bandgap reference voltage using a folded amplifier setup with PMOS transistors in a common-gate configuration, which eliminates the need for duplicate lateral resistors and allows operation under low power supply voltage, reducing silicon area and improving power supply rejection ratio (PSRR).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large resistors are used to generate CTAT current in existing bandgap reference circuits, then the current inversion temperature compensation is achieved, but the silicon area occupied increases significantly
Solution Approach 1:
The patent changes the resistance value parameter to a moderate range (1kΩ to 100kΩ) rather than using very large resistors, and compensates by adjusting the current mirror ratio and core resistor values to achieve the same temperature compensation effect with smaller area occupation
Solution Approach 2:
The patent combines the CTAT current generation function with the existing PTAT current path by using current mirrors to replicate and scale currents, merging multiple functions into shared circuit structures rather than using separate large resistors for each current path
2Reliability
If cascoded current mirrors are used to improve power supply rejection ratio, then PSRR is enhanced, but the device complexity and number of components increase
Solution Approach 1:
The patent segments the current mirror structure into modular units with standardized configurations, allowing PSRR enhancement through controlled replication rather than complex cascoded structures, reducing overall circuit complexity while maintaining rejection performance
Solution Approach 2:
The patent introduces dynamic biasing and control mechanisms that allow the current mirrors to adapt their operation mode based on power supply conditions, achieving high PSRR through dynamic adjustment rather than static complex cascoded structures
3Manufacturing precision
If duplicate lateral resistors are used at each terminal of the core to balance currents, then current matching is improved, but the silicon area and device complexity increase considerably
Solution Approach 1:
The patent uses current mirror technology to create accurate current copies without requiring physical resistor duplication, achieving current matching through transistor-based current replication which occupies significantly less area than duplicate lateral resistors
Solution Approach 2:
The patent designs universal current mirror structures that serve multiple functions simultaneously: current copying, current matching, and automatic balancing across different terminals, eliminating the need for separate duplicate resistors at each terminal
4Use of energy by moving object
If conventional bandgap reference circuits are designed to operate with low current consumption, then power efficiency is improved, but the required power supply voltage increases to minimum or higher levels
Solution Approach 1:
The patent optimizes operating parameters including transistor bias points, current mirror ratios, and resistor values to achieve low current consumption at reduced power supply voltages, moving away from conventional high-voltage low-current operating points
Solution Approach 2:
The patent implements dynamic voltage and current regulation that adapts operating conditions in real-time, allowing the circuit to maintain low power consumption across varying supply voltages and to operate efficiently at minimum supply voltage levels
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves stable output signals with low current consumption and reduced silicon area, enabling operation under minimum power supply voltage while maintaining high PSRR, thus addressing the inefficiencies of previous circuits.
Implementation Method 1
a first fed-back amplifier possessing at least one first stage arranged as a folded setup and comprising first PMOS transistors arranged according to a common-gate setup
Implementation Method 2
the voltage across the terminals of a diode or of a transistor mounted in diode fashion traversed by a current such as a PTAT current, is a voltage comprising a term inversely proportional to absolute temperature
Implementation Method 3
The step of summing is performed in the feedback stage of the first amplifier
Data Source
AI summary
A circuit includes a first PMOS transistor that includes a first PMOS source coupled to a first input node, a first PMOS gate, and a first PMOS drain. A second PMOS transistor includes a second PMOS source coupled to a second input node, a second PMOS gate, and a second PMOS drain coupled to the second PMOS gate. A first resistor coupled between the first PMOS source and a ground node. A first diode element coupled between the first resistor and the ground node and a second diode element coupled between the second PMOS source and the ground node. A third PMOS transistor includes a third PMOS gate, a third PMOS source coupled to a supply node, and a third PMOS drain coupled to the first input node. A fourth PMOS transistor includes a fourth PMOS gate coupled to the third PMOS gate, a fourth PMOS source coupled to the supply node, and a fourth PMOS drain coupled to the second input node.