Bandgap Ready Circuit for RFID Tags
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Solution Overview
Problem
Passive RFID tags using EEPROM memory are inadequate for high-throughput applications due to slow data transfer rates and instability in challenging environments, particularly with variations in temperature and intermittent power supply from RFID readers.
Innovation Solution
A bandgap ready circuit for RFID tags is introduced, featuring a bandgap circuit for voltage regulation, comparators for monitoring voltages, and a logic circuit to provide a bandgap ready logic signal, ensuring stable operation and efficient power management using FRAM memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If EEPROM memory is used in passive RFID tags, then the tags can operate without external power sources, but the data transfer rate is slow and cannot meet high-throughput application requirements
Solution Approach 1:
The patent changes the memory technology parameter from EEPROM to FRAM (Ferroelectric Random Access Memory), which provides both high-speed operation and non-volatile storage capabilities, enabling high-throughput applications while maintaining passive tag operation
Solution Approach 2:
The patent implements dynamic power management and voltage regulation circuits that adapt to varying RF power levels, allowing the FRAM-based tag to operate reliably despite intermittent and variable power supply from the RFID reader
2Productivity
If FRAM memory is used to increase data throughput, then high-speed data transfer is achieved, but the circuit becomes more sensitive to power supply variations and environmental conditions
Solution Approach 1:
The patent implements feedback control circuits including voltage regulators and power management circuits that continuously monitor and adjust operating parameters, compensating for power supply variations and environmental conditions to maintain stable FRAM operation
Solution Approach 2:
The patent incorporates protective circuits and power conditioning stages before the FRAM memory to cushion against harmful effects of power variations and environmental stress, preventing damage and ensuring reliable high-speed operation
3Use of energy by moving object
If passive RFID tags operate without batteries, then power consumption is minimized, but the available power supply is intermittent and unstable due to reliance on RF energy harvesting
Solution Approach 1:
The patent implements self-powered operation where the RFID tag harvests energy from the RF field and uses it to power all onboard circuits including FRAM memory, voltage regulators, and communication interfaces, eliminating batteries while maintaining operational reliability through intelligent power management
Solution Approach 2:
The patent changes the power supply parameter from battery-based stable voltage to RF-harvested variable voltage, and implements circuitry that adapts to this changing parameter through dynamic voltage regulation and power management
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the operational robustness and data transfer rates of RFID tags by providing a temperature-compensated voltage supply, reducing power consumption, and preventing overshoot in power supply voltages, thus enabling reliable performance in demanding environments.
Implementation Method 1
a bandgap circuit for providing a bandgap voltage
Implementation Method 2
a first comparator for monitoring first and second voltages in the bandgap circuit and for providing a first logic signal
Data Source
AI summary
A bandgap ready circuit for an RFID tag includes a bandgap circuit for providing a bandgap voltage, a first comparator for monitoring first and second voltages in the bandgap circuit and for providing a first logic signal, a second comparator for monitoring third and fourth voltages in the bandgap circuit and for providing a second logic signal, and a logic circuit for combining the first and second logic signals to provide a bandgap ready logic signal.