Bandgap Reference Circuit With Low-Bias Leakage Control
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Solution Overview
Problem
The leakage problem of MOS devices becomes significant at high temperatures exceeding 125°C, affecting the performance of analog circuits in automotive-grade chips.
Innovation Solution
A reference voltage generation circuit comprising a biasing and voltage-limiting circuit, a PTAT current generation circuit, a zero-temperature coefficient reference voltage generation circuit, and a start-up circuit, which operates under low substrate bias conditions to minimize leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If MOS devices operate at high temperatures exceeding 125°C, then the chip can function in harsh automotive environments, but leakage current increases significantly affecting analog circuit performance
Solution Approach 1:
The patent changes the substrate bias parameter from high to low conditions. By operating the MOS devices under low substrate bias, the leakage current is significantly reduced while maintaining functionality at high temperatures. This parameter change directly addresses the contradiction by modifying the operating conditions rather than the device structure itself.
Solution Approach 2:
The patent applies preliminary anti-action by pre-establishing low substrate bias conditions before leakage becomes problematic. The circuit design incorporates biasing mechanisms that proactively maintain low substrate potential, preventing the accumulation of leakage current that would otherwise occur at high temperatures, thus protecting analog circuit performance in advance.
2Device complexity
If conventional reference voltage circuits are used, then the circuit design is simple, but the minimum operating voltage is limited and leakage is not effectively controlled
Solution Approach 1:
The reference voltage generation circuit is segmented into distinct functional modules: a PTAT current generation circuit that operates under low substrate bias, a zero-temperature coefficient reference voltage generation circuit, and a biasing and voltage-limiting circuit. This segmentation allows each module to be optimized independently, achieving both low leakage and expanded voltage range without excessive overall complexity.
Solution Approach 2:
The patent introduces a PTAT (proportional to absolute temperature) current as an intermediary element. This PTAT current serves as a mediator between the temperature-dependent leakage effects and the reference voltage generation, allowing the circuit to compensate for temperature effects and expand the operating voltage range while maintaining control over leakage current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively addresses the leakage problem of MOS devices at high temperatures, ensuring stable performance of analog circuits and overcoming limitations on minimum operating voltage.
Implementation Method 1
a proportional to absolute temperature (PTAT) current generation circuit... the PTAT current generation circuit is configured to generate a PTAT current
Implementation Method 2
a zero-temperature coefficient reference voltage generation circuit comprises a second resistor and a bipolar junction transistor... superposed with a negative temperature coefficient voltage between the base electrode and the emitter electrode of the bipolar junction transistor
Implementation Method 3
the first branch circuit and the second branch circuit forming a current mirror, the first branch circuit comprising a first P-channel MOS transistor and a first N-channel MOS transistor, and the second branch circuit comprising a second P-channel MOS transistor and a second N-channel MOS transistor... a gate of the first P-channel MOS transistor is connected to a gate of the second P-channel MOS transistor
Data Source
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AI summary
The present invention provides a reference voltage generation circuit (30) and an automotive-grade chip. The reference voltage generation circuit (30) includes a biasing and voltage-limiting circuit (34), a PTAT current generation circuit (31), a zero-temperature coefficient reference voltage generation circuit (32), and a start-up circuit (33). The PTAT current generation circuit (31) includes a first P-channel MOS transistor (MP1), a second P-channel MOS transistor (MP2), a first N-channel MOS transistor (MN1), a second N-channel MOS transistor (MN2), and a first resistor (R1). An output end of the start-up circuit (33) is connected to a drain of the first N-channel MOS transistor (MN1). The biasing and voltage-limiting circuit (34) is connected to the drain of the first N-channel MOS transistor (MN1) to limit an operating voltage of the first N-channel MOS transistor (MN1). The zero-temperature coefficient reference voltage generation circuit (32) includes a second resistor (R2) and a bipolar junction transistor (B1). A PTAT current generated by the PTAT current generation circuit (31) flows through the second resistor (R2) to generate a PTAT voltage, and the PTAT voltage is superposed with a negative temperature coefficient voltage between a base electrode and an emitter electrode of the bipolar junction transistor (B1) to generate a zero-temperature coefficient reference voltage.