Bandgap Reference Voltage Circuit Offset Compensation
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Solution Overview
Problem
Existing bandgap circuits in CMOS analog integrated circuits face limitations due to the offset voltage of the operating amplifier, which affects the precision of the reference voltage, and previous solutions either increase the number of PNP transistors or adjust the current mirror ratios, leading to increased circuit area and complexity.
Innovation Solution
The proposed solution incorporates a reference voltage circuit with a first amplifier, load devices, PN junction devices, an offset voltage reduction circuit, a coupling node potential takeout circuit, and an area adjustment circuit to minimize the offset voltage effect by adjusting the emitter area of the PN junction devices and using switches to trim the resistance ratio, thereby improving the precision of the bandgap voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of PNP transistors is increased to reduce offset voltage effect, then the precision of reference voltage is improved, but the circuit area increases
Solution Approach 1:
The patent adjusts the emitter area of the PNP transistor (Q2) as a variable parameter to compensate for offset voltage effects. By making the emitter area adjustable rather than fixed, the circuit achieves precise reference voltage without requiring multiple transistors, thus resolving the contradiction between precision and area.
Solution Approach 2:
The patent performs preliminary adjustment of the emitter area during the manufacturing process to pre-compensate for offset voltage. This preliminary action eliminates the need for additional transistors to compensate for offset effects during operation, reducing circuit area while maintaining precision.
2Measurement precision
If the current mirror ratio is adjusted to reduce offset voltage effect, then the precision of bandgap voltage is improved, but the device complexity increases
Solution Approach 1:
The patent changes the emitter area parameter of the PNP transistor to compensate for offset voltage effects rather than adjusting current mirror ratios. This single parameter change approach simplifies the circuit structure and reduces device complexity while achieving the desired precision improvement.
3Measurement precision
If the emitter area of PNP transistor is adjusted to compensate for offset voltage, then the precision of reference voltage is improved, but the manufacturing process complexity increases
Solution Approach 1:
The emitter area adjustment is performed as a preliminary action during the manufacturing process. By establishing the correct emitter area upfront, the patent eliminates the need for complex post-manufacturing adjustments or additional compensation circuits, actually simplifying the overall manufacturing process while improving precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the impact of offset voltage on the bandgap voltage, allowing for precise adjustment and stabilization of the reference voltage without significantly increasing the circuit area or complexity, thus enhancing the precision and reliability of the bandgap circuit.
Implementation Method 1
a first amplifier (AMPBM1), which includes first and second input terminals (IP, IM), coupled to a first power source line (VDP5) and a second power source line (GND), and configured to output a reference voltage
Implementation Method 2
the potential of a forward-biased PN junction and a voltage proportional to the absolute temperature (T)
Implementation Method 3
The offset voltage reduction circuit is configured to reduce an offset voltage between the first and second input terminals at the first amplifier
Implementation Method 4
the coupling node potential takeout circuit is configured to take out potentials of the first and second coupling nodes
Implementation Method 5
The area adjustment circuit is configured to adjust an area of the second PN junction device in accordance with the potentials of the first and second coupling nodes which are taken out by the coupling node potential takeout circuit
Data Source
AI summary
A reference voltage circuit includes a first amplifier, a first load device and a first PN junction device, second and third load devices and a second PN junction device, an offset voltage reduction circuit, a coupling node potential takeout circuit, and an area adjustment circuit. The offset voltage reduction circuit is configured to reduce an offset voltage between the first and second input terminals at the first amplifier, and the coupling node potential takeout circuit is configured to take out potentials of the first and second coupling nodes. The area adjustment circuit is configured to adjust an area of the second PN junction device in accordance with the potentials of the first and second coupling nodes which are taken out by the coupling node potential takeout circuit.