Bandwidth-Aware Logical Edge Placement on Reconfigurable Processors
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Solution Overview
Problem
Existing compilers for reconfigurable processors, particularly coarse-grained reconfigurable architectures (CGRAs), struggle to optimize the performance and resource utilization of highly-parallel applications like machine learning and artificial intelligence workloads due to the lack of effective cost estimation tools for guiding the compilation process, leading to inefficiencies in dataflow graph implementation.
Innovation Solution
A cost estimation tool is developed to estimate the realized bandwidth consumption of logical edges between producer and consumer units during placement and routing on reconfigurable processors, aiding the compiler in optimizing hardware resource allocation and synchronization for high-performance implementation of parallel applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing compilers are used for reconfigurable processors without cost estimation tools, then the compilation process is simpler, but the performance and resource utilization of highly-parallel applications deteriorate
Solution Approach 1:
The cost estimation tool performs preliminary analysis during the compilation process to estimate bandwidth consumption of logical edges before final placement and routing decisions are made. This allows the compiler to optimize resource allocation and synchronization in advance, improving performance without requiring complex post-compilation adjustments.
Solution Approach 2:
The cost estimation tool provides feedback to the compiler about estimated bandwidth consumption and resource utilization during compilation. This feedback mechanism enables the compiler to adjust placement and routing strategies to optimize performance for highly-parallel applications while managing compilation complexity through automated decision-making.
2Productivity
If cost estimation tools are implemented to optimize placement and routing, then resource utilization improves, but computational overhead increases
Solution Approach 1:
The cost estimation tool implements partial estimation by focusing computational effort on critical paths and high-bandwidth logical edges within the dataflow graph. Rather than exhaustively analyzing all possible placements and routings, the tool estimates costs for the most impactful decisions, improving resource utilization while limiting computational overhead to manageable levels.
3Measurement precision
If accurate bandwidth consumption estimation is performed for all logical edges, then placement and routing optimization improves, but estimation time and complexity increase
Solution Approach 1:
The cost estimation tool applies local quality by providing detailed and accurate bandwidth consumption estimates for critical logical edges that significantly impact performance, while using simplified estimation methods for less critical edges. This selective approach maintains high measurement precision where needed while reducing overall estimation time and complexity.
Data Source
AI summary
The present application describes a system with a cost estimation tool for placing and routing a logical edge onto a reconfigurable processor and a method of operating such a cost estimation tool. The method comprises receiving an operation unit graph comprising the logical edge between a logical producer unit and a logical consumer unit and a tentative assignment of the logical edge, the logical producer unit, and the logical consumer unit to a physical link, a physical producer unit, and a physical consumer unit of the reconfigurable processor. The method further comprises determining a realized bandwidth consumption of the tentative assignment based on determining an upper bandwidth limit of the logical edge, determining an end-to-end bandwidth, determining a scaling factor of the realized bandwidth, and determining congestion estimation of the physical link.