Bandwidth Matching Assembler Disassembler Cell Architecture
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Solution Overview
Problem
There is a need for a device or method that can efficiently match the bandwidth of peripheral devices to a computer system, ensuring data transmission occurs at optimal rates for both the system and the devices, particularly when the peripheral devices operate at lower bandwidths than the system.
Innovation Solution
A bandwidth matching device comprising an assembler and a disassembler that transforms incoming data streams of a given bandwidth into a concatenated output with a larger bandwidth, utilizing a stepped arrangement of cells and multiplexers to process multiple inputs simultaneously, and subsequently disassembles the concatenated output back into the original data streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted from a peripheral device operating at lower bandwidth to a memory operating at higher bandwidth, then data transmission speed can be increased, but the complexity of the transmission system increases due to bandwidth matching requirements
Solution Approach 1:
The bandwidth matching device is divided into multiple cells arranged in a stepped configuration, where each cell processes one bit of data at a time. This segmentation allows the system to handle bandwidth mismatch by processing data in discrete, manageable units through the stepped cells, reducing the overall complexity while achieving higher transmission speeds.
Solution Approach 2:
The patent introduces a temporal dimension by using clock cycles to sequentially present data through the stepped cells. Instead of attempting to transmit all data simultaneously (which would increase complexity), the system transmits data bit-by-bit across multiple time steps, effectively managing bandwidth mismatch without proportionally increasing system complexity.
2Productivity
If multiple incoming data streams are processed simultaneously to increase output bandwidth, then data processing efficiency improves, but the device complexity increases due to the need for multiple multiplexers and cells
Solution Approach 1:
Multiple incoming data streams are merged into a single concatenated output stream through the stepped arrangement of cells and multiplexers. By combining multiple input streams in a systematic manner, the device achieves higher output bandwidth while the structured merging process keeps the complexity manageable through predictable resource allocation.
Solution Approach 2:
The multiplexers are configured to select and route data from multiple input streams in advance, preparing the data for concatenation in the stepped cells. This preliminary selection and routing action enables efficient processing of multiple streams simultaneously without requiring complex real-time decision-making during the data transmission process.
3Adaptability or versatility
If data is sequentially presented to stepped cells on each clock cycle, then bandwidth matching is achieved, but the time required for data transmission increases
Solution Approach 1:
The stepped cells continuously process data on each clock cycle without idle periods, maintaining constant useful action throughout the transmission process. This continuous operation ensures that bandwidth matching is achieved efficiently while minimizing the total transmission time by keeping all cells actively engaged in data processing from the first clock cycle through the final cycle.
Data Source
AI summary
Broadly speaking, a bandwidth matching device is provided for transforming a number of incoming data streams each having a first bandwidth into an outgoing data stream having a second bandwidth. More specifically, the bandwidth matching device provides an assembler and a disassembler. The assembler incorporates a stepped arrangement of cells for transforming the number of incoming data streams having a given bandwidth into an outgoing data stream having a larger bandwidth, wherein each portion of the outgoing data stream represents a concatenation of a number of portions of each of the incoming data streams. As a complement to the assembler, the disassembler uses a stepped arrangement of cells to transform the concatenated output generated by the assembler back into the number of incoming data streams originally received by the assembler.