Bandwidth Scaling Transmitter for Variable Clock Processing Elements
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Solution Overview
Problem
Modern processing units with variable clock rates often experience a bandwidth mismatch with conventional high-speed interconnects, leading to inefficiencies as the interconnect's fixed clock rate cannot be easily adjusted, resulting in either excessive bandwidth delivery or buffer overruns.
Innovation Solution
A method is implemented where a processing element scales its bandwidth by interleaving discardable data with non-discardable data blocks, using a serial mask to determine when to transmit discardable values, allowing communication across interconnects with fixed bandwidths, and a receiver scales the data back down to match its own bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the interconnect operates at a fixed high clock rate, then the interconnect bandwidth is maintained, but the processing element cannot receive data fast enough causing buffer overruns
Solution Approach 1:
The data stream is segmented into individual data values that can be transmitted separately. The transmitter breaks down continuous data flow into discrete units that can be paced according to the processing element's capabilities, while the interconnect maintains its high-speed operation.
Solution Approach 2:
Data transmission occurs in periodic cycles rather than continuously. The transmitter sends data values at intervals that match the processing element's clock rate, allowing the interconnect to operate at higher speeds while the receiver processes data at its own pace without buffer overruns.
2Use of energy by moving object
If the processing element operates at a lower variable clock rate to conserve power, then power consumption is reduced, but bandwidth mismatch occurs with the fixed-rate interconnect
Solution Approach 1:
The transmitter acts as an intermediary between the interconnect and processing element. It receives high-speed data from the interconnect and retransmits at the processing element's lower variable clock rate, enabling power-saving operation without bandwidth mismatch.
Solution Approach 2:
The transmission parameters (clock rate, data rate) are dynamically changed by the transmitter to match the processing element's variable operating conditions. When the processing element reduces clock rate for power saving, the transmitter adjusts its output rate accordingly.
3Reliability
If large buffers are used to prevent buffer overrun, then data transmission reliability improves, but device complexity and resource requirements increase
Solution Approach 1:
The buffering function is extracted from the processing element and implemented in the transmitter. This eliminates the need for large buffers at the receiver, reducing device complexity while maintaining transmission reliability through controlled data pacing.
4Productivity
If complex credit systems are implemented to manage bandwidth, then bandwidth allocation accuracy improves, but device complexity increases
Solution Approach 1:
The transmitter automatically adjusts its data transmission rate based on the processing element's variable clock rate without requiring complex credit management. The system self-regulates bandwidth allocation through direct clock rate matching, eliminating the need for complex credit systems.
Data Source
AI summary
A transmitter is configured to scale up a low bandwidth delivered by a first processing element to match a higher bandwidth associated with an interconnect. A receiver is configured to scale down the high bandwidth delivered by the interconnect to match the lower bandwidth associated with a second processing element. The first processing element and the second processing element may thus communicate with one another across the interconnect via the transmitter and the receiver, respectively, despite the bandwidth mismatch between those processing elements and the interconnect.