Bang-Bang Detector Coding for Low-Complexity Clock Recovery
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Solution Overview
Problem
Existing clock recovery circuits require high-frequency digital-to-analog converters (DACs) with a large number of bits, leading to signal addition in the analog domain and prolonged phase error information, which is difficult to implement effectively.
Innovation Solution
A clock recovery circuit that digitally samples a source signal at 4 times the base clock frequency, converts the samples into binary numbers using a coding mechanism, and provides an analog control signal to a voltage-controlled oscillator (VCO) through a bank of ADCs and current mirrors, reducing the need for high-frequency DACs and simplifying the circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a DAC with a large number of bits operates at high frequency, then the clock recovery circuit can process high-speed data streams, but the circuit complexity and implementation difficulty increase significantly
Solution Approach 1:
The patent segments the single high-resolution DAC into multiple low-resolution DACs (e.g., four 1.5-bit DACs), each handling a portion of the phase error information. This segmentation allows each DAC to operate at lower complexity while collectively achieving the required performance through parallel operation at quarter the clock frequency.
Solution Approach 2:
The patent transitions from time-domain multiplexing to a spatial/parallel dimension by using multiple DACs operating simultaneously at reduced frequency. Instead of one DAC cycling through multiple phases at high frequency, multiple DACs operate in parallel at quarter frequency, fundamentally changing the operational dimension from temporal to spatial.
2Speed
If individual DACs are used for each phase detector, then the system can operate at lower frequencies, but signal addition must occur in the analog domain and phase error information is elongated for an undesirable length of time
Solution Approach 1:
The patent introduces digital adders as intermediary components that combine the outputs of multiple phase detectors in the digital domain before feeding to the DACs. This digital intermediary eliminates the need for analog signal addition and resolves the phase error elongation issue by providing clean digital summation at the appropriate timing.
3Speed
If time-domain multiplexing circuitry is used to combine phase-error signals, then the DAC can operate at high frequencies, but the implementation becomes difficult and complex
Solution Approach 1:
The patent inverts the conventional approach by using multiple low-frequency DACs instead of a single high-frequency DAC. Rather than trying to make one DAC operate at high frequency through time-domain multiplexing, the solution uses four DACs operating at quarter frequency, fundamentally inverting the frequency-scaling approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides an inexpensive and capable clock recovery system that obviates the challenges of high-speed DACs, ensuring efficient clock recovery with reduced operational complexity and increased resolution.
Implementation Method 1
a voltage-controlled oscillator (VCO) controlled by the analog output of the DAC circuit and adapted to produce a base clock having a base clock frequency
Implementation Method 2
converting the two separate streams of binary numbers into a single analog output using a positive current mirror and a negative current mirror
Data Source
AI summary
Various apparatus and methods for related to clock recovery are disclosed. For example, in one illustrative embodiment, a clock recovery circuit includes a coding circuit adapted to translate a stream of first digital numbers derived from a source signal into a stream of first binary numbers and a stream of second binary numbers, a digital-to-analog converter (DAC) circuit coupled to the coding circuit and configured to provide an analog output based on the streams of first and second binary numbers and a voltage-controlled oscillator (VCO) controlled by the analog output of the DAC circuit and adapted to produce a base clock having a base clock frequency.