Bang-Bang DFLL Wakeup Timer for Low-Voltage Stable IoT Timing
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Solution Overview
Problem
Existing wakeup timers for IoT remote wireless sensor nodes face challenges in achieving low power consumption, small area occupation, and long-term stability while operating at low supply voltage, due to limitations in RC oscillators and analog-intensive frequency-locked loops.
Innovation Solution
A digital-intensive frequency-locked loop (DFLL) architecture with a bang-bang frequency detector, digital loop filter, and low-power high-resolution self-biased Sigma Delta digitally-controlled oscillator (DCO) is employed, utilizing a chopped dynamic comparator and multi-phase clock generator to achieve low area, low power, and low supply voltage operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RC oscillators or analog-intensive frequency-locked loops are used for wakeup timing, then the timer can be implemented on-chip without quartz crystals, but the power consumption increases and long-term stability deteriorates
Solution Approach 1:
The patent replaces analog-intensive frequency-locked loop circuits with a digital-intensive frequency-locked loop (DFLL) architecture. This substitution uses digital logic elements (flip-flops, multiplexers, counters) instead of analog oscillators and filters, achieving ultra-low power consumption (259 nA) while maintaining excellent long-term stability (Allan deviation floor below 20 ppm) through digital signal processing and feedback control mechanisms.
Solution Approach 2:
The patent employs a bang-bang frequency detector that operates by comparing the phase difference between the input signal and a reference signal, using digital control words to adjust the DCO frequency. This parameter-based digital control approach enables precise frequency regulation with minimal power consumption, achieving both low power (259 nA) and high stability (20 ppm Allan deviation) simultaneously.
2Area of stationary object
If advanced CMOS processes are utilized to reduce area and power, then the timer occupies minimal area and consumes low power, but maintaining long-term stability becomes more difficult
Solution Approach 1:
The patent implements a fully digital DFLL architecture in 40 nm CMOS process, replacing analog components with digital logic circuits. This enables ultra-compact area occupation (0.07 mm²) while achieving excellent long-term stability (Allan deviation below 20 ppm) through digital signal processing, demonstrating that advanced digital CMOS technology can simultaneously achieve small size and high reliability.
Solution Approach 2:
The patent employs a self-biased Sigma Delta DCO that automatically adjusts its operating point and compensation parameters based on process variations and aging effects. This self-calibration mechanism enables the timer to maintain stable performance (20 ppm Allan deviation) without external trimming or calibration circuits, achieving both minimal area (0.07 mm²) and high stability in advanced CMOS processes.
3Reliability
If quartz crystals are used to achieve accurate wakeup timing, then long-term stability is improved, but area occupation increases and cost increases
Solution Approach 1:
The patent replaces quartz crystal oscillators with a fully integrated digital-intensive frequency-locked loop that generates accurate wakeup timing signals on-chip. This substitution eliminates the need for external quartz crystals, achieving wakeup timing accuracy (Allan deviation below 20 ppm) while occupying minimal area (0.07 mm²) and reducing system cost.
4Use of energy by moving object
If the supply voltage is reduced to achieve ultra-low power consumption, then power consumption decreases, but maintaining frequency stability and avoiding noise becomes more difficult
Solution Approach 1:
The patent implements a digital-intensive frequency-locked loop that operates reliably at ultra-low supply voltage (0.7 V). The digital logic-based frequency detector and Sigma Delta DCO maintain stable operation and frequency control at this low voltage, achieving ultra-low power consumption (259 nA) while maintaining frequency stability through digital feedback control, avoiding the noise and stability issues that plague analog circuits at low voltage.
Data Source
AI summary
The present disclosure describes systems and methods to provide a digital wakeup timer with reduced size and lower power. An example system or apparatus includes a wakeup timer employing a digital-intensive frequency-locked loop (DFLL) architecture to fully utilize the advantages of advanced CMOS processes. Such a system includes a bang-bang frequency detector, a digital loop filter, a digitally-controlled oscillator (DCO), and a multi-phase clock generator. An output of the bang-bang frequency detector is provided to an input of the digital loop filter. An output of the digital loop filter is provided to the DCO. An output of the DCO includes information indicative of an output frequency. The multi-phase clock generator provides respective clock signals based on the output frequency to the bang-bang frequency detector, the digital loop filter, and the DCO.