Bang-Bang DPLL Phase Correction for Fast Lock and Low Jitter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Digital phase-locked loops (DPLLs) with bang-bang phase detectors face a trade-off between output jitter and lock time, as they only provide information on the sign of phase error, leading to slow lock times and high jitter, and more complex linear detectors are needed to correct phase errors but are not scalable.
Innovation Solution
A circuit with a single-bit phase detector, a sign detector, a counter, and a mapping function that increases the phase correction level based on consecutive data strings, allowing for faster phase correction and reduced jitter by detecting the length of data strings and applying a phase correction level through a summer block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a bang-bang phase detector is used in a digital PLL, then the circuit complexity is reduced and scalability is improved, but the lock time increases and output jitter increases
Solution Approach 1:
The patent applies preliminary action by pre-charging the integrator capacitor to a voltage corresponding to the maximum phase correction level before phase detection begins. This allows the PLL to immediately apply maximum correction when a phase error is detected, significantly reducing lock time without increasing circuit complexity. The pre-charged state is prepared in advance, enabling rapid response to phase errors.
Solution Approach 2:
The patent implements dynamics by making the phase correction level variable rather than fixed. The correction level dynamically adjusts based on the detected phase error magnitude and direction, allowing the system to apply stronger corrections when needed and smaller adjustments when approaching lock. This dynamic adjustment reduces overall lock time while maintaining low jitter near the locked state.
2Device complexity
If a bang-bang phase detector is used in a digital PLL, then the circuit complexity is reduced, but the output jitter increases
Solution Approach 1:
The patent applies feedback by continuously monitoring the phase difference between reference and feedback signals and adjusting the phase correction level accordingly. The integrator continuously integrates the phase error signals, and the system automatically reduces correction magnitude as phase alignment improves, minimizing jitter near the locked state. The feedback loop ensures smooth transitions and prevents excessive corrections that would increase jitter.
3Loss of time
If the response to BBPD output is increased for fast locking, then the lock time is reduced, but the output jitter increases
Solution Approach 1:
The patent implements dynamics by making the phase correction level variable rather than fixed. The correction level dynamically adjusts based on the detected phase error magnitude and direction, allowing the system to apply stronger corrections when needed and smaller adjustments when approaching lock. This dynamic adjustment reduces overall lock time while maintaining low jitter near the locked state.
Solution Approach 2:
The patent applies feedback by continuously monitoring the phase difference between reference and feedback signals and adjusting the phase correction level accordingly. The integrator continuously integrates the phase error signals, and the system automatically reduces correction magnitude as phase alignment improves, minimizing jitter near the locked state. The feedback loop ensures smooth transitions and prevents excessive corrections that would increase jitter.
Data Source
Figure 1
Figure 2
Figure 3a
AI summary
The present invention relates to a gigitaol phaselocked loop DPLL (300, 400) having a phase-to-digitalP2D (60) with an enhanced bang-bang phase detector BBPD. Such a P2D (60) comprises a BBPD (62), an additional digital circuit (200) including a sign detector (210), a counter (220) and a mapping function (230), and a summer block (64). During the locking process, the BBPD (62) may- output a repeating value, namely a string of data bits of same polarity value either "+1" or "-1". The polarity sign is detected by the sign detector (210), and the data string length is determined by the counter (220) that is reset to zero whenever the BBPD output changes sign. The mapping function (230) is configured for mapping the data string length in input to the phase correction level in output Its output is added to that of the BBPD (62) through the summer block (64), such that the phase correction level is increased to enhance the locking process whenever a data string is detected.