Bank-Aware Multi-Bit Trie Memory Distribution
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Solution Overview
Problem
Existing multi-bit trie data structures in network processing units face bank collisions due to uneven distribution of memory accesses across memory banks, which can lead to reduced performance, especially in scenarios where randomness and statistical distribution assumptions are invalid or not applicable, particularly in hardware with strict performance guarantees and limited on-chip memory.
Innovation Solution
Implementing a bank-aware multi-bit trie that distributes mtrie levels across multiple memory banks, ensuring all mtrie nodes in a given block are stored in the same bank and subsequent mtrie blocks are stored in different banks, thereby evenly distributing memory accesses across banks and minimizing bank collisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If mtrie nodes are stored in contiguous memory blocks, then space efficiency is improved, but bank collisions increase due to uneven distribution of memory accesses across banks
Solution Approach 1:
The patent divides the mtrie structure into multiple blocks distributed across different memory banks. Specifically, it segments the mtrie such that different levels or subsets of nodes are placed in different banks, allowing parallel access to multiple banks during lookup operations and reducing bank collision conflicts
Solution Approach 2:
The patent applies local quality by storing mtrie nodes with similar access patterns together in the same memory bank while distributing different access patterns across different banks. This ensures that frequently accessed nodes are localized in specific banks, improving cache utilization and reducing bank collision for those access patterns
2Productivity
If mtrie blocks are distributed across different memory banks, then bank collisions are reduced, but memory access complexity increases
Solution Approach 1:
The patent performs preliminary action by pre-computing and storing the mapping between mtrie node addresses and their corresponding memory bank locations during the construction phase. This pre-computed mapping information is embedded in the data structure, allowing the lookup operation to directly determine which bank to access without complex runtime calculations
Solution Approach 2:
The patent introduces an intermediary mapping layer between the mtrie logical structure and the physical memory banks. This intermediary structure translates logical node addresses to physical bank locations, simplifying the access pattern by providing a direct translation mechanism rather than requiring complex address calculation and bank selection logic
Data Source
AI summary
Embodiments of the invention include a method performed by a bank aware mtrie control module for distributing a plurality of mtrie levels across a plurality of memory banks. The bank aware mtrie control module identifies the plurality of memory banks present and identifies one or more mtrie blocks in one or more mtrie levels, each mtrie block is an array of mtrie nodes associated with an mtrie level. The bank aware mtrie control module stores each mtrie block in one of the plurality of memory banks, all mtrie nodes in a given mtrie block are stored in the same memory bank. For each subsequent mtrie level, the bank aware mtrie control module ensures that each of the mtrie blocks in that mtrie level is stored in one of the plurality of memory banks other than the memory bank storing mtrie blocks of an immediately previous mtrie level.