Bank Interleaving Controller Power Management

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Solution Overview

Problem

Bank interleaving techniques increase power consumption when accessing multiple memory banks simultaneously, limiting the number of banks that can be used and hindering memory processing speed, even when sufficient power is available to perform additional write operations.

Innovation Solution

A bank interleaving controller with a power calculator and write driver that compares data bit values to determine only changed bits for writing, calculating total power consumption and enabling write operations only when within a reference power threshold, allowing flexible bank usage and expanded write bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If bank interleaving techniques are used to access multiple memory banks simultaneously, then data processing speed is improved, but power consumption increases

Engineering Contradiction:
Improvedata processing speedVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent changes the operational parameters of memory banks by dynamically selecting which banks to activate based on available power consumption capacity. The power manager monitors power usage and adjusts the number of active banks accordingly, allowing the system to optimize between speed and power consumption by varying the activation state of different banks rather than maintaining a fixed configuration

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces dynamic control of bank activation through a power manager that continuously monitors power consumption and adjusts bank usage in real-time. This dynamic approach allows the memory system to adapt its performance characteristics based on current power availability, enabling flexible trade-offs between data processing speed and power consumption rather than being constrained by static bank configurations

Inventive Principle:
Principle #15Dynamics

2Productivity

If the number of active memory banks is increased to improve processing speed, then data processing speed is improved, but the number of banks that can be used is limited by power consumption

Engineering Contradiction:
Improvedata processing speedVSAvoidnumber of usable banks
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent changes the operational parameters of memory banks by dynamically selecting which banks to activate based on available power consumption capacity. The power manager monitors power usage and adjusts the number of active banks accordingly, allowing the system to optimize between speed and power consumption by varying the activation state of different banks rather than maintaining a fixed configuration

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces dynamic control of bank activation through a power manager that continuously monitors power consumption and adjusts bank usage in real-time. This dynamic approach allows the memory system to adapt its performance characteristics based on current power availability, enabling flexible trade-offs between data processing speed and power consumption rather than being constrained by static bank configurations

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10185510B2Bank interleaving controller and semiconductor device including the same
Publication Date: 2019.01.22 SK HYNIX INC
  • US10185510B2 patent drawing
  • US10185510B2 patent drawing
  • US10185510B2 patent drawing

AI summary

A bank interleaving controller may include a power calculator and a write driver. The power calculator may calculate a total power consumption by adding a power consumption of one or more memory banks that are performing write operations and an amount of power that is expected to be additionally consumed to write input data. The write driver may write the input data to a memory cell corresponding to an input address when the total power consumption is equal to or less than a reference power consumption.