Bank Selection Control Block for Semiconductor Integrated Circuit Signal Load Reduction
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Solution Overview
Problem
Conventional semiconductor integrated circuits face challenges in high-speed operation due to signal delay and increased current consumption caused by the large load on global input/output lines, especially as chip sizes increase, leading to difficulties in achieving low power consumption.
Innovation Solution
A semiconductor integrated circuit design that selectively provides global input/output line control signals only to a selected bank block, reducing the load on global input/output lines by using a bank selection control block to manage up and down bank even/odd numbered global line control signals and SDRAM write global signals in response to read control signals and bank information, allowing for reduced current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If global input/output lines are shared by all banks to enable data transmission, then data reading/writing function is achieved, but signal load and current consumption increase
Solution Approach 1:
The patent segments the global input/output lines into bank-specific lines by introducing a bank selection control block that generates separate control signals for different bank blocks (first bank block and second bank block). This allows each bank to have dedicated GIO lines instead of sharing a common set, thereby reducing the load on individual lines and lowering current consumption while maintaining data transmission capability.
Solution Approach 2:
The patent applies local quality by providing separate global input/output lines to different bank blocks based on their specific operation requirements. The bank selection control block generates distinct control signals (e.g., GIO_CTRL_1, GIO_CTRL_2) for different banks, enabling each bank to operate with optimized, bank-specific GIO lines rather than a uniform shared structure, thus reducing overall signal load and power consumption.
2Productivity
If global input/output lines are shared by all banks, then data transmission function is achieved, but signal delay occurs during toggling
Solution Approach 1:
The patent segments the shared GIO lines into dedicated lines for different bank blocks. The bank selection control block generates separate control signals for each bank, which isolates the signal paths and eliminates the signal delay caused by toggling across all shared lines. This segmentation allows each bank to toggle its dedicated GIO lines independently, significantly improving signal speed.
3Quantity of substance
If chip size increases to improve integration capacity, then storage capacity is improved, but global input/output line length increases causing signal delay
Solution Approach 1:
The patent addresses the increased chip size by segmenting the GIO lines into bank-specific lines controlled by the bank selection control block. This segmentation reduces the effective length of signal paths for each bank, preventing signal delay even as the overall chip size increases to accommodate greater integration capacity.
Data Source
AI summary
A semiconductor integrated circuit according to one embodiment can include an up bank block that includes a first group of banks, a down bank block that includes a second group of banks, and a bank selection control block that provides up and down bank even-numbered global line control signals, up and down bank odd-numbered global line control signals, and up and down bank SDRAM write global line control signals in response to first and second group read control signals and a bank information signal in the up bank block and the down bank block. In this case, the bank selection control block may respond to a DDR signal and an SDR signal that are provided from an MRS (Mode Register Set).