Banked Load-Store Unit Queue Segmentation

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Solution Overview

Problem

Load-store units in processors face limitations in queue size due to timing constraints, and existing solutions with multiple load/store units are less efficient and harder to manage as separate logical entities.

Innovation Solution

Implementing a load-store unit with banked queues, where each queue is subdivided into multiple banks with logic circuitry controlling pointers for memory ordering, allowing for interleaved entry management and retirement selection based on eligibility and address translation status, while maintaining a single logical entity view for software.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the queue size in a load-store unit is increased, then the number of stored memory instructions increases, but the timing constraints are violated

Engineering Contradiction:
Improvequeue sizeVSAvoidtiming constraints
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The queue is divided into multiple banks (e.g., bank 0, bank 1, etc.), where each bank can be independently managed with its own pointer logic. This segmentation allows the overall queue capacity to increase while each individual bank maintains manageable timing characteristics, resolving the contradiction between large queue size and timing constraints.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If multiple load/store units are implemented to increase queue capacity, then the total queue size increases, but the device complexity and manageability worsen

Engineering Contradiction:
Improvequeue capacityVSAvoidmanageability
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

Multiple banks are merged into a single logical queue entity that is managed by one load-store unit. The pointer logic in each bank exchanges information to maintain unified queue behavior, allowing large capacity without the complexity of managing multiple separate units. Software sees a single logical queue rather than multiple independent units.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Each bank's pointer logic performs multiple functions: managing its own bank's entries, exchanging pointer information with other banks, and participating in unified queue operations. This multi-functionality allows the system to achieve large queue capacity through a single unified management approach rather than requiring multiple specialized units.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Quantity of substance

If a single logical queue is subdivided into multiple banks, then the queue capacity increases with reduced timing impact, but the circuit area overhead increases

Engineering Contradiction:
Improvenumber of entriesVSAvoidcircuit area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The queue is segmented into multiple banks that can be spatially distributed or organized in a memory-efficient manner. This segmentation allows the total number of entries to increase while managing the circuit area through organized placement and shared resources among banks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The pointer logic is designed to be universal across all banks, with each instance performing the same set of functions for its respective bank. This universality allows for efficient resource sharing and reduces overall circuit area compared to having completely independent management logic for each bank.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10133571B1Load-store unit with banked queue
Publication Date: 2018.11.20 APPLE INC
  • US10133571B1 patent drawing
  • US10133571B1 patent drawing
  • US10133571B1 patent drawing

AI summary

A load-store unit having one or more banked queues is disclosed. In one embodiment, a load-store unit includes at least one queue that is subdivided into multiple banks. Although divided into multiple banks, the queue logically appears to software as a single queue. A first bank of the queue includes a first plurality of entries, with the second bank of the queue having a second plurality of entries, wherein each of the entries is arranged to store memory instructions. Each of the banks is associated with corresponding logic circuitry that controls one or more pointers for that bank. The pointer information may be exchanged between the logic circuits associated with the banks. Based on the pointer information that is exchanged, each bank may output (e.g., for retirement) one entry per cycle.