Banked Memory Architecture for High-Speed Data Stream Storage
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Solution Overview
Problem
In computer systems, there is a challenge in efficiently receiving and storing high-speed sequential data streams while preserving the order of data elements, as existing memory solutions often require high-speed and large-capacity memory elements that are costly and silicon-intensive, making it difficult to balance performance and device size.
Innovation Solution
The use of banked memory architecture, where incoming data is distributed across multiple memory elements, reducing the speed and size requirements of each memory element, and utilizing control information to reconstruct the data stream in the correct sequence, even if the first element is not stored in the first memory bank.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single high-speed memory element is used to store incoming data streams, then the data stream can be received and stored quickly, but the memory element requires expensive high-speed operation and significant silicon space
Solution Approach 1:
The patent divides the single high-speed memory requirement into multiple lower-speed memory banks. Instead of using one memory element operating at high speed to handle the entire data stream, the system segments the data stream and distributes it across N memory banks, each operating at 1/Nth the speed of the original requirement. This segmentation resolves the contradiction by maintaining overall productivity while reducing the speed complexity of individual memory elements.
2Quantity of substance
If large amounts of memory are incorporated to store significant amounts of data, then storage capacity increases, but the memory bandwidth requirement becomes difficult to achieve
Solution Approach 1:
The patent segments both the storage capacity requirement and the bandwidth requirement across multiple memory banks. Each bank handles a portion of the total storage capacity and a corresponding portion of the bandwidth. This allows the system to achieve large total storage capacity while each individual bank operates at manageable bandwidth speeds, resolving the contradiction between quantity of storage and speed of access.
Solution Approach 2:
The patent introduces a new dimension of parallelism by using multiple memory banks operating simultaneously. Instead of increasing bandwidth in a single dimension, the system distributes data across multiple banks in parallel, effectively adding a dimensional aspect to the storage architecture. This allows large storage capacity to be achieved without proportionally increasing the bandwidth requirement of any single memory element.
3Reliability
If the memory element operates at more than twice the incoming data rate, then the memory can empty itself while simultaneously receiving new data, but such high-speed memories are expensive and silicon-intensive
Solution Approach 1:
The patent segments the reliability requirement across multiple memory banks. Instead of requiring a single memory element to operate at more than twice the data rate to ensure continuous data availability, the system distributes the data stream across N banks, each operating at reduced speeds. The control logic tracks which bank contains the next required data element, ensuring continuous reliable data delivery while each bank operates at manageable speeds, thus resolving the contradiction between reliability and device complexity.
Data Source
AI summary
The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and size of the input buffers used to receive the data streams. This allows the device to employ large, relatively slow memory elements, thereby permitting large amounts of sequential data to be stored by the receiving device. Using control information that was written as the data was being stored in the memory banks, a reordering element is later able to retrieve the data elements from the plurality of memory banks, in an order that is different from that in which the stream was received, and to reassemble the data stream into the original sequence.