Banked Physical Register Data Flow Architecture for Out-of-Order Processors
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Solution Overview
Problem
Conventional out-of-order processor architectures face challenges in increasing instruction throughput without significant increases in size and power dissipation, while maintaining efficient execution and retirement of instructions in program order.
Innovation Solution
The proposed method involves assigning age tags to instructions, allocating physical registers, and using a reorder buffer to execute instructions out of order while maintaining program order for retirement, allowing for simultaneous execution of multiple instructions without increasing the processor's size or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock frequency and issue width are increased to improve single thread performance, then instruction throughput is improved, but processor size and power dissipation increase significantly
Solution Approach 1:
The processor divides the execution pipeline into multiple issue widths (e.g., 2-way, 4-way, 8-way) that can be selectively activated. This segmentation allows the processor to achieve high instruction throughput when needed while consuming less power when operating at lower issue widths, thus resolving the contradiction between throughput and power dissipation.
Solution Approach 2:
The processor dynamically adjusts its issue width and execution resources based on workload requirements. By making the issue width configurable and adjustable, the processor can optimize performance for specific tasks while minimizing power consumption during normal operation, effectively managing the trade-off between throughput and power dissipation.
2Productivity
If issue width is increased to execute more instructions per clock cycle, then instruction throughput is improved, but processor size increases significantly
Solution Approach 1:
The execution units and resource allocation logic are segmented into modular components that can be selectively instantiated. This allows the processor to achieve high issue widths when needed while maintaining a compact core design, resolving the contradiction between throughput and processor size.
Solution Approach 2:
The processor employs universal execution units and shared resources that can handle multiple instruction types and issue widths. This multi-functionality allows a single processor design to achieve high throughput without requiring separate dedicated hardware for each issue width, thus avoiding significant size increases.
3Productivity
If out-of-order execution is implemented to improve throughput, then instruction execution efficiency is improved, but maintaining program order for retirement becomes more complex
Solution Approach 1:
The patent introduces an intermediary structure (such as a reorder buffer or retirement queue) that decouples the out-of-order execution engine from the in-order retirement mechanism. This intermediary maintains the mapping between executed instructions and their original program order, simplifying the retirement process while preserving execution efficiency.
Solution Approach 2:
The processor uses age tags or priority values as parameters to track instruction retirement order. By changing the parameter representation from direct program counter sequencing to age-based or priority-based tagging, the system manages retirement complexity more effectively while maintaining out-of-order execution benefits.
Data Source
AI summary
Instructions to be executed by a processing system are fetched from a memory. Respective age tags are assigned to the instructions such that each of the age tags indicates an age of the corresponding instruction in the processing system. A respective physical register is allocated to each destination logical register referenced by each instruction. The respective age tags assigned to the instructions are written to respective physical registers allocated to the destination logical registers of the instructions, and to a buffer configured to maintain a program order of the instructions. The instructions are executed by the processing system. Executing the instructions includes executing at least some of the instructions in an order different from the program order of the instructions. The age tags in the buffer are used to retire executed instructions in a same order as the program order of the instructions.