Power Semiconductor Package With Bar Vias For Reduced Parasitic Inductance
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Solution Overview
Problem
Conventional power semiconductor packages face challenges with high costs and time-consuming processes due to the use of laser vias for connections, which have limited current carrying capability and require precise alignment, hindering efficient thermal and electrical performance.
Innovation Solution
A power semiconductor package is developed using bar vias embedded in a support substrate, allowing for enhanced current carrying capacity and easier connectivity, with the active region of the semiconductor die facing upwards for improved routing and thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If laser vias are used to make connections between the active region and passive components, then electrical connections are established, but the current carrying capability is limited and the process is costly and time consuming
Solution Approach 1:
The patent changes the physical parameters of the connection structure by replacing laser vias with bar-shaped conductive traces that have larger cross-sectional area and different geometry. This parameter change enables higher current carrying capability while simplifying the manufacturing process and reducing costs.
Solution Approach 2:
The patent replaces the laser via formation process (which requires precise laser drilling and filling operations) with a conventional trace deposition process. This substitution eliminates the need for complex laser processing equipment and reduces manufacturing complexity.
2Reliability
If the active region is faced down toward the printed circuit board, then connections are made through the substrate, but high precision alignment is required and thermal dissipation is hindered
Solution Approach 1:
The patent inverts the conventional packaging approach by facing the active region upward toward the printed circuit board instead of downward. This inversion eliminates the need for through-substrate vias and precise alignment, as the active region directly interfaces with the PCB for both electrical connections and thermal dissipation.
3Area of stationary object
If laser vias with small diameter are used, then space is saved, but current carrying capability is limited
Solution Approach 1:
The patent transitions from vertical via connections (one-dimensional through-substrate paths) to planar trace connections (two-dimensional surface paths). This dimensional change allows the conductive traces to achieve larger effective cross-sectional area for current carrying while maintaining compact layout through optimized trace routing.
Data Source
AI summary
A semiconductor package includes an output inductor placed over a support substrate, a power semiconductor die having a bottom surface situated on the support substrate and a top surface having an active region, where the output inductor is coupled to the active region on the top surface of the support substrate, and where the support substrate includes a plurality of bar vias. The output inductor is a packaged component having at least two leads in electrical connection with the active region of the power semiconductor die. The support substrate further includes routing conductors in electrical connection with the active region of the power semiconductor die. The power semiconductor die includes a control transistor and a sync transistor connected in a half-bridge.